CROSS Ted Hess, Digital Equipment Corporation author Joseph M. Newcomer, Carnegie-Mellon University documentation 19 February 1981 The material used in this specification, including but not limited to construction times and operating speeds, is for informational purposes only. All such material is subject to change without notice. Consequently DEC makes no claim and shall not be liable for its accuracy. This document describes the operational procedures for CROSS, an assembler which operates on the DECsystem-10/20 systems, translating source code for 6502, 6800, 6805, 6809, 8080, 8085, MCS-48, Z80, 1802, 3870/F8[future], and 8008 micro-processors into binary files suitable for absolute load. All of the appendices to this manual and the index were constructed by Joseph M. Newcomer, Carnegie-Mellon University Computer Science Department. The information for the appendix on object formats is derived from information contributed by Ted Hess, but the current editor takes responsibility for any inaccuracies which may have crept in during the transcription. Additional work has been done on CROSS by Mark L. Sproul and Mel J. Pleasant at Rutgers University. CROSS-Microcomputer cross assembler 1 1. Introduction CROSS is an assembler which operates on the DECsystem-10/20 and assembles code for many currently available micro-processors. With the exception of the variations listed in this manual, CROSS implements the features of the PDP-11 macro assembler for RSX-11D. No attempt was made to provide source compatibility between CROSS and other micro- processor assemblers. Rather, CROSS has been designed to provide consistent, powerful features for all of the mnemonics associated with each micro-processor. Numerous people have worked on CROSS over the years; appropriate credits are recorded in the change log of the source. While CROSS is designed to be language compatible with the MACRO-11 language, its PDP-10 operating environment necessitates a PDP-10 style operating procedure. Expression evaluation has been updated to provide the following features: - Default radix is decimal. - @ indicates octal radix, same as to ^O - % indicates binary (6502/6800/6809 only), same as to ^B - %nn indicates register value nn (all others) - $ indicates hexadecimal radix - ^H indicates hexadecimal radix - ^ indicates that the evaluated expression is to be divided by 256. (high byte) - \ indicates that the evaluated expression is to be taken modulo 256 (low byte). The assembler makes two passes over the source, outputting the binary and listing files during pass two and appending a symbol or cross reference table to the listing file. PDP-10 memory is dynamically allocated for large symbol table storage and macro storage. Introduction CROSS-Microcomputer cross assembler 2 2. Syntax differences The syntax of CROSS is more compatible with that of MACRO-11 than that of most manufacturer's assemblers. This means that you will not be able to compile straight 8080, Z80, 6502 or 6800 code with this assembler. However, the transliterations are reasonably straightforward and are described for each machine in the appendices. In general, you must specify registers with a %- directive. The machine which differs most from the manufacturer's specification of an assembler syntax is the Zilog Z80. This is because CROSS implements the Z80 syntax as a superset of the 8080 syntax. Consequently, the syntax of most operations follows that of the 8080. In addition, some Z80 mnemonics conflicted with 8080 mnemonics; the Z80 has been assigned new mnemonics where these conflicts existed. Any Z80 operation which has no 8080 counterpart has also been assigned a mnemonic; some correspond to the Zilog specification (wherever this was possible) and most do not. Consequently, a complete cross- reference between the Zilog syntax and the CROSS transliteration has been provided. Syntax differences CROSS-Microcomputer cross assembler 3 3. Operating procedures 3.1. Loading CROSS CROSS is run by typing the monitor command: @CROSS ;tops20 .R CROSS ;tops10 3.2. Initial dialogue When the assembler is ready to accept the user's command string, it types an asterisk. The user must now type the command string on the same line. The general form of the command string is: binary output, listing output = source input(s) In addition, the command(s) may be stored in a file (default extension .CCL) and read in by specifying: @filename Each input/output specification consists of the group: dev:filnam.Ext[proj.,prog.]/switch:arg - dev is: DSK for disk PTR for paper tape reader PTP for high speed punch TTY for the user's terminal LPT for a queued line printer - If not specified, the device is assumed to be the disk. Other system devices may also be used, depending upon the system configuation. - filnam is the file name of the appropriate file. - ext is the file name extension for that file. If is not specified, the assumptions are: binary string: .BIN (absolute) listing string: .LST source string: .M05 Motorola 6805 Operation CROSS-Microcomputer cross assembler 4 .M48 Intel MCS-48 family .M65 MOS Technology/Synertek/Rockwell 6502 .M68 Motorola 6800 .M69 Motorola 6809 family .M80 8080/Z80/8085 .M88 8008, 8080 mnemonics .M08 8008 , Intel mnemonics .M18 CPD1802, COSMAC .MF8 Fairchild F8/Mostek 3870 [future] - [proj.,prog.] is the project-programmer number assigned for the disk area to be used. If not specified, the user's local area is assumed. Once specified, the number pair becomes the new default assumption for the following files. (Use translate command on TOPS20). At CMU, the CMU PPN format is accepted. - Switches are specified by preceding each with a slash character. Switch arguments are preceded by colons. In addition to explicit specifications of the switches, a default set of switches may be specified with a SWITCH.INI file (chapter 6, page 13). /M05 source is Motorola 6805 code /M48 source is Intel MCS-48 code /M65 source is 6502 code /M68 source is Motorola 6800 code /M69 source is Motorola 6809 code /M80 source is Intel 8080, Intel 8085 or Zilog Z80 code /M88 source is 8008 using 8080 compatible mnemonics /M08 source is Intel 8008 original Intel mnemonics /M18 source is 1802 code (RCA COSMAC) /MF8 source is Fairchild F8/Mostek 3870 [future] /LI simulate .LIST directive (see chapter 4). /NL simulate .NLIST directive (see chapter 4). Operation CROSS-Microcomputer cross assembler 5 /EN simulate .ENABL directive (see chapter 5). /DS simulate .DSABL directive (see chapter 5). /CRF append cross reference table to the listing files (see chapter 4). /PTP binary output is ASCII coded hex. This switch takes an optional format type as a parameter, as /PTP:fmt. The format types are: COS Uses RCA COSMAC format (see section XV.1.1) INT Uses Intel Intellec (CP/M .HEX) format. KIM Uses MOS Technology format with start address in the last record (this was the default CROSS format for a long time). MOS Uses MOS Technology format with record count in last record. MOT Uses Motorola Exorcisor format (S1 and S9 records) If no argument is specified, the format is based upon the language input type determined by the file extension: Extension PTP Format .M65 MOS .M68,.M69 MOT .M80,.M08,.M88,.M48 INT .M18 COS .MF8 KIM (future) /N suppress error messages and expanded summary to the terminal. /OCT listing format in octal - hex is default /I output binary in image mode (one byte per 36 bit PDP- 10 word). This switch must be used to copy directly to paper tape. /P pack binary output. This is the default case and the switch is not needed. /CDR simulate card reader input. This is actually Operation CROSS-Microcomputer cross assembler 6 independent of the physical input device but causes the assembler to ignore all characters on a column after the 72nd. /SOL sequence output lines (see chapter 4). /GNS generate new source (see chapter 4). /NSQ suppress listing of PDP-10 style seq. Numbers. /EQ equate the following symbols to zero. This is a method for introducing conditional arguments without creating special parameter tapes. "/EQ:sym1:sym2" is the equivalent of the source statements "sym1=0" and "sym2=0". /LEN set the page length for the output listing. /WID set the page width for the output listing. Operation CROSS-Microcomputer cross assembler 7 4. Listing control CROSS has two categories of listing controls: MACRO-11 compatible, which may be specified either in source statements or in the command string, and a superset which is limited to the command string. 4.1. Source statement listing control Listings are controlled at source statement level through the use of the .LIST and .NLIST directives. These are complementary in that any function which can be enabled by a .LIST can be disabled by a .NLIST. To reduce redundancy, the following descriptions will emphasize the .LIST while implying the .NLIST complement. The following are the allowable arguments for the .LIST directive along with the default settings (li for .LIST and nl for .NLIST): The first group controls intra-line listing. Suppression of any of these will cause the assembler to utilize the space by moving the remainder of the line over. SEQ list the sequence numbers. These numbers represent the source line numbers and are replaced by the nesting level in parentheses for generated lines (macros, etc.). LOC list the value of the location counter. BIN list the binary code generated by the assembler. SRC list the source statement. This is included primarily for completeness. COM list the comment field. BEX list binary code which requires more than one listing line. suppression of this is particularly useful in reducing the length of listing required for long .ASCII strings. The following arguments pertain to entire statements: MB list macro binary and call only - no source MD list macro definitions. MC list macro calls. ME-nl list macro expansions. The default causes the expansion to be suppressed in the interest of supply economy. ME controls all generated text (.MACROs, .REPTs, and .IRPs). Caution - due to their dual nature, .REPTs and .IRPs qualify both as definitions and calls. CROSS treats MD and MC as a pair in these cases, suppressing the listing if either is set. .LIST/.NLIST CROSS-Microcomputer cross assembler 8 CND list conditionals. Suppression causes unsatisfied conditionals and all conditional directives (whether satisfied or not) to be not listed. SYM append a symbol table to the listing file. TTM list in terminal format (one column of binary to a line, truncation after 72 columns). Default setting is determined by the output device specified: enabled if the physical device is TTY: and disabled (line printer mode) in all other cases. TOC-nl list a table of contents during pass one. This consists of the .SBTTL directives being listed at the beginning of the listing file. Each line consists of the line number and all text to the right of the .SBTTL directive. LD-nl list listing directives. Specifically, this causes all .LIST/.NLIST directives which have no arguments to be listed. its primary use is in debugging listing control. .LIST and .NLIST directives with no arguments perform an over- ride function. They control a listing "level" which is decremented for each .NLIST and incremented for each .LIST. The level count is used as a three way switch: 1. Zero (initial condition): no special action. 2. Less than zero: unconditionally suppress the listing except for lines containing errors. 3. Greater than zero: list unconditionally. .LIST/.NLIST are normally paired to return the level count to zero. the .NLIST/.LIST sequence is used to suppress a range which is normally listed, while the .LIST/.NLIST sequence is used to over-ride a range which is normally suppressed, such as in a macro expansion. The level count allows macro expansions to use the listing control and return it to its previous state. 4.2. Command string equivalents The command string contains the equivalent of all the above .LIST and .NLIST functions as well as some that are not available at source level. Indeed, many of the source level arguments are of primary interest at command string level but can be used in the source to modify default settings. The command string equivalents of .LIST and .NLIST are /LI and /NL, respectively. Arguments are specified by preceding them with colons. Thus /NL:bex:cnd is the equivalent of .NLIST CND,BEX. In all cases, command string switches override their source level equivalents (as well as previous occurrences in the command string). Effectively, specification of a function in a command string will cause all its source level equivalents (and their complements) to be ignored. i.e. /LI:me would enable the listing of macro expansions and cause all ".LIST/.NLIST ME" directives to .LIST/.NLIST CROSS-Microcomputer cross assembler 9 be ignored. /LI (no arguments) causes everything to be listed, while /NL suppresses the listing of all but error lines, the symbol table, and the cross reference tables. 4.3. Other listing controls The following swithces are specified in output side of the command string by preceding the mnemonic by a slash: /OCT list in octal - default is hex /N suppress error messages to the terminal (unless it is also the listing device). /CRF append a cross reference table to the listing file. CROSS accomplishes this in the following manner: 1. The listing file is generated in the normal way during pass two, using the name specified by the user. 2. Simultaneously, a temporary file (xxxCRF.TMP, where xxx is the job number) is created. This contains encoded cref information. 3. At the end of pass two, the temporary file is read and the cref information is integrated into the symbol table. 4. The references are appended to the listing file. if insufficient core was available to build the table, the process is repeated. When through, the temporary file is deleted. The cross reference table format is as follows: 1. The symbol itself. 2. Its symbol table value, unless .NLIST sym was specified. Therefore the symbol table itself is always pre-empted. 3. All references to the symbol, except that no more than one reference to a given source line will be listed. symbols in generated text always refer to the previous source line. 4. Defining occurrences are flagged with a "#". 5. Destructive references are flagged with a "*". These are defined to be all symbols encountered in .LIST/.NLIST CROSS-Microcomputer cross assembler 10 op-code fields which store into a memory location or a register. 6. As many references per listing line as possible, depending upon the "ttm" mode, are used. This can be increased by suppressing "sym". /SOL Sequence output lines. Listings are normally source oriented: 1. Sequence numbers reflect the source line number. 2. Macro expansion lines have their nesting level, in parentheses, in the sequence number field. 3. Lines containing nothing but a form feed are not listed but cause the sequence number to be incremented. 4. Page numbers reflect physical input pages (incremented only upon encountering a form feed). Pages forced by the assembler have a -n to reflect an extension page. i.e. If the assembler had encountered 3 form feeds and was on its third listing page since the last one, it would be "page 4-2". when /SOL is specified, listings are output oriented: 1. Listed lines have consecutive numbers, except for binary extensions. 2. Page numbers reflect the number of pages listed. /GNS Generate a new source. This causes the listing file to take on the appearance of a source file. specifically, it: 1. Suppresses the listing of headers, error flags, summary blocks, and any other output over which the user otherwise would have no control. 2. Simulates a /NL:seq:loc:bin:bex:me. 3. therefore, by itself, it recreates the source file. Normal usage would have supplementary switches following it. i.e. /gns/nl:md:mc /li:me would replace macros, repeats, and irps by their generated code, /gns/nl:cnd would purge conditionals, and /gns/li:seq would be an expensive way of creating a sequence numbered listing of the source file. /LEN:num Sets the page length to the specified number. This allows the user to take advantage of longer page formats for some .LIST/.NLIST CROSS-Microcomputer cross assembler 11 printers, or to produce listings suitable for viewing a page at a time on a video terminal. At CMU, the default length is 80, for the Dover using SAILA8. The normal default is 58. /WID:num Sets the page width to the specified number. This allows the user to take advantage of wider page formats, or get presentable listings on devices which have narrower margins, such as home microcomputer printers. At CMU, the default width is 120, for the Dover using SAILA8. The normal default is 132. .LIST/.NLIST CROSS-Microcomputer cross assembler 12 5. Enable/Disable control As an alternative to the proliferation of directives, CROSS uses one complementary pair, .ENABL/.DSABL, with arguments. Their command string equivalents are /EN and /DS. The relationship between command string and source statement specification, as well as their argument specification, is the same as in .LIST/.NLIST. M85 allow 8085 opcodes (RIM/SIM) in .M80 files Z80 allow Z80 opcodes in .M80 files FPT floating point truncation. ".ENABL FPT" is equivalent to ".TRUNC" while ".DSABL FPT" is equivalent to ".ROUND". ABS absolute assembly AMA absolute memory addressing NPP ".ENABL NPP" causes suppression of the output of the following code, while ".DSABL NPP" causes its resumption. ERF error flags can be selectively suppressed (or enabled) by specifying ERF, directly followed by the selected error characters. "/ds:ERFzm" would cause "m" and "z" errors to be ignored, "/ds:ERF" would cause all errors to be ignored, and "/en:ERFa" would cause"a" flags (argument errors) to be flagged. LC lower case to upper case translation of input; the default is .ENABL LC so listings contain output in the same case as it was input. LSB local symbol block TIM timing information - causes number of states to be output on the listing. Alas, for most machines this data is not entered in the internal tables. REG default register names .ENABL/.DSABL CROSS-Microcomputer cross assembler 13 6. User-defined switch defaults CROSS is capable of accepting user-defined switch defaults. Any switches that are valid in a command string may be specified in a special file called SWITCH.INI. When CROSS is run, it will look for this file in the user's directory. At CMU, the logical device HOM: is checked, and if a SWITCH.INI file is found there, it will be used instead of the one on the aliased or connected 1 directory. If the file is not found, then standard defaults (as defined elsewhere in this document) are assumed. If SWITCH.INI is found, but no CROSS switches are found, default settings are assumed. To specify defaults, use the editor of your choice to create a file called SWITCH.INI. This file must contain a line of the following format: CROSS/switch1/switch2...../switchn continuation lines are permitted. Specifically, a line containing a terminal hyphen is assumed to be followed by a continuation line. Of course CROSS does not consider the hyphen to be a part of any switch. Note that this feature is a subset of the facility offered normally by use of SWITCH.INI files. 1 At CMU on TOPS-20, the logical device HOM: can be assigned to the user's login directory by the LOGIN.CMD file. SWITCH.INI CROSS-Microcomputer cross assembler 14 7. Macro libraries Macro libraries are used by the .MCALL directive. As in Macro-11, the format is: .MCall arg1,arg2,... where the arguments are macro names required for the program. However, CROSS recognizes that users may wish to have different libraries for different machines, but a single user may be using CROSS for several different machines at the same time. Therefore, instead of the simple rule that SYSMAC.SML is used, if it exists, and then trying SYS:SYSMAC.SML, CROSS uses language- dependent libraries. The extension of the library is the appropriate extension for the language being compiled. Thus, if you have a file whose extension, for reasons known only to yourself, is ".M80" but which contains 6809 code, and you have overridden the default language selection with a /M69 switch, the macro library will have extension ".M69". The extensions are the default extensions discussed on page 3, and in the rules below are indicated by language. The search rules are thus: DSK:SYSMAC.SML DSK:SYSMAC.language SYS:SYSMAC.SML SYS:SYSMAC.language SWITCH.INI CROSS-Microcomputer cross assembler 15 I. General notation Each section of an appendix describes one aspect of a given machine I.1. Machine State This section defines the registers or other status of the machine, including condition code bits. This status is referred to in the descriptions of the instructions, and thus may include status or registers which cannot be specified in the syntax to CROSS. I.2. Notation This section describes the notation used in the description of the operations. For example, a set of instructions might all use registers R1, P2, C3 and D4, or immediate data. This collection might be called src-opnd, thus reducing the number of cases which need to appear in the opcode list. These names, and other notations, appear here. I.3. Syntax Here, the actual CROSS representation details, particularly when they differ from those of the manufacturer's standard assembler, are discussed. The names of locations, registers, operands, etc. which correspond to machine state which can be referred to are given here. I.4. Opcodes Here, the complete list of mnemonics are given. This list, the syntax section, and the notation section should allow one to write actual CROSS code. The comments in the opcode list describe the operation; while not intended to replace the manufacturer's or other reference manual, they do provide a quick check on what is happening. The semantics are expressed either as comments, or as fragments of code in the Bliss language. In Bliss, the "." operator means "contents of", and a name stands for its "address". Thus, a description such as A = .A + 1 means that register (or location) A gets the contents of register (or location) A plus 1. Bit fields are indicated by <> pairs, of the form . Thus, .A<1,4> means the contents of the register (or location) named by A<1,4>, i.e., bits 1 thru 5. Bit 0 is the low order bit. Multibyte and other complex fields are indicated by catenation, the | operator; thus, the HL register pair of the 8080 is indicated by %H|%L. Boolean truth and falsehood is determined by the value of the low-order bit of the expression used as the boolean; thus 0, 2, 4, 6, etc. are all "false" SWITCH.INI CROSS-Microcomputer cross assembler 16 values. The following table gives the operation names used for the descriptions of the instructions and explanations of their meanings. and bitwise and ash arithmetic shift, positive values shift left, negative values shift right geq greater than or equal, signed, two's complement gequ greater than or equal, unsigned gtr greater than, signed, two's complement gtru greater than, unsigned leq less than or equal, signed, two's complement lequ less than or equal, unsigned lss less than, signed, two's complement lsh logical shift, positive values shift left, negative values shift right. lssu less than, unsigned, two's complement not bitwise complement or bitwise or rot rotate, positive values are rotate left, negative values are rotate right xor bitwise exclusive or + two's complement add - two's complement subtract * two's complement multiply <=> swap; the contents of the two locations named are swapped. SWITCH.INI CROSS-Microcomputer cross assembler 17 II. 8080 syntax II.1. Machine State The registers for the 8080 are defined as: - %A - the accumulator - %B - register B - %C - register C - %D - register D - %H - register H, high-order memory reference register - %L - register L, low-order memory reference register - %SP - the stack pointer register - %PSW - the processor status, or F register Register pairs are written in the description of each instruction by concatenating two names with a vertical bar, e.g., %H|%L is the 16-bit value in the HL register pair. Parentheses are sometimes added for visual clarity, e.g., ".(%H|%L)". The flags in the status register are represented by: - c - the carry bit - p - the parity bit. True if the last operation had odd parity, false if even parity. - z - the zero bit. True if the last operation had a zero result. - s - the sign bit. True if the last operation had a negative result. - ie - the interrupt enable flag. In each description of an instruction that alters the condition codes, either an explicit assignment is written (e.g., "c=0") or the condition codes are listed in curly brackets. In this case, it is implied that c is set to indicate carry or borrow (arithmentic operations), z is set if the result is zero, s is set if the result is negative, and p is set if the parity is even. II.2. Notation To reduce the size of the description, several notational conventions will be established for desribing the operands: - i - represents an immediate operand which is 8 bits wide. - m - represents a memory operand which is 16 bits wide. - M - represents an implied memory operand addressed by the register pair %H|%L. - MEM - represents all of addressible memory. - DEV - represents all addressible devices. - v - a special 3-bit value used for the RST instruction - opnd - a general operand, either register or implied memory. For registers, it will be expressed as %r for one of the 8-bit registers, and for memory it will be expressed as M in the instruction syntax 8080 CROSS-Microcomputer cross assembler 18 and MEM[.(%H|%L)] in the description of the instruction. - %rp - a register pair from the set {%B|%C, %D|%E, %H|%L %SP}. These would be written, in the assembler, as %B, %D, %H or %SP. - %rpn - a register pair from the set {%PSW, %A, %B|%C, %D|%E, %H%L}. - Written as %PSW, %SP, %B, %D or %H. II.3. Syntax - %A,%B,%C,%D,%E,%H,%L - 8-bit registers - %PSW,%SP,%B,%D,%H - where appropriate, 16-bit registers - M - memory, addressed via %H|%L - Immediate data is represented by the expression which generates it II.4. Opcodes The opcodes that are recognized for the 8080 are shown below. The function is given in a BLISS-like notation (the dot operator means "contents of"). ACI i %A = .%A + i + .c; {c,z,s,p} ADC opnd %A = .%A + opnd + .c ADD opnd %A = .%A + .opnd; {c,z,s,p} ADI i %A = .%A + i; {c,z,s,p} ANA opnd %A = .%A and .opnd; c = 0; {z,s,p} ANI i %A = .%A + i; c = 0; {z,s,p} CALL m MEM[.%SP-1], MEM[.%SP-1] = .pc; %SP = .%SP - 2; pc = m; CC m if .c then CALL m CM m if .s then CALL m CMA %A = not .%A; {note: c,z,s,p not changed} CMC c = not .c CMP opnd .%A - .opnd; {c,z,s,p} CNC m if not .c then CALL m CNZ m if not .z then CALL m CP m if not .s then CALL m CPE m if .p then CALL m CPI i .%A - i; {c,z,s,p} CPO m if not .p then CALL m CZ m if .z then CALL m DAA %A = DecimalAdjust(.%A); {c,z,s,p} DAD %B %H|%L = .(%H|%L) + .(%B|%C); {c} DAD %D %H|%L = .(%H|%L) + .(%D|%E); {c} DAD %SP %H|%L = .(%H|%L) + .%SP; {c} DCR opnd opnd = .opnd - 1; {z,s,p} DCX %rp %rp = .(%rp) - 1 DI ie = 0 EI ie= 1; HLT IN i %A = .DEV[i]; INR opnd opnd = .opnd + 1; {z,s,p} 8080 CROSS-Microcomputer cross assembler 19 INX %rp %rp = .(%rp) + 1; JC m if .c then pc = m; JM m if .s then pc = m; JMP m pc = m; JNC m if not .c then pc = m; JNZ m if not .z then pc = m; JP m if not .s then pc = m; JPE m if .p then pc = m; JPO m if not .p then pc = m; JZ m if .z then pc = m; LDA m %A = .MEM[m]; LDAX %B %A = .MEM[.(%B|%C)]; LDAX %D %A = .MEM[.(%D|%E)]; LHLD m %H = .MEM[m]; %L = .MEM[m+1]; LXI %rp,m %rp = m; MOV %r1,%r2 %r1 = .%r2; MOV m,%r MEM[m] = .%r; MOV %r,m %r = .MEM[m]; MVI opnd,i opnd = i; NOP ; ORA opnd %A = .%A or .opnd; c = 0; {z,s,p} ORI i {%A = .%A or i;}; c = 0; {z,s,p} OUT i DEV[i] = .%A; PCHL pc = .(%H|%L); POP %rpn %rpn = .MEM[.%SP], .MEM[.%SP + 1]; %SP = .%SP + 2; PUSH %rpn %SP = .%SP - 2; MEM[.%SP], MEM[.%SP + 1] = .%rpn; RAL c|%A = .(c|%A) lsh 1; RAR c|%A = .(c|%A) lsh -1; RC if .c then RET; RET pc = .MEM[.%SP], .MEM[.%SP+1]); %SP=.%SP + 2; RLC c = .%A<7,1>; %A = .%A lsh 1 RM if .s then RET; RNC if not .c then RET; RNZ if not .z then RET; RP if not .s then RET; RPE if .p then RET; RPO if not .p then RET; RRC c = .%A<0,1>; %A = .%A lsh -1; RST v CALL v lsh 8; RZ if .z then RET; SBB opnd %A = .%A - .opnd - .c; {c,z,s,p} SBI i %A = .%A - i - .c; {c,z,s,p} SHLD m MEM[m] = .%H; MEM[m+1] = .%L; SPHL %sp = .(%H|%L); STA m MEM[m] = .%A; STAX %B MEM[.(%B|%C)] = .%A; STAX %D MEM[.(%D|%E)] = .%A; STC c = 1; SUB opnd %A = .%A - .opnd; {c,z,s,p} SUI i %A = .%A - i; {c,z,s,p} XCHG %D <=> %H; %E <=> %L; XRA opnd %A = .%A xor .opnd; c = 0; {z,s,p} 8080 CROSS-Microcomputer cross assembler 20 XTHL MEM[.%SP - 1] <=> %H; MEM[.%SP] <=> %L; 8080 CROSS-Microcomputer cross assembler 21 III. Z80 syntax III.1. Introduction The Z80 portion of CROSS is not intended to correspond to the Zilog syntax; instead, it is treated as an extension of the 8080 operations described in section II. This means that new opcode designators have been invented where appropriate. III.2. Machine State The Z80 registers are designated exactly like the 8080 registers, with the following additions: - %X - index register X (16 bits) - %Y - index register Y (16 bits) - iv - the interrupt vector base address (8 bits) - ra - the dynamic RAM refresh address (8 bits) III.3. Notation The following notational extensions are made to the 8080 description: - b - A bit position, 0-7, for bit operations - opnd - In addition to %r and M, indexed operands are permitted for all instructions which use opnd; these are expressed to the assembler as d(X) or d(Y), where d is an 8-bit displacement. In the description, they are interpreted as ".%X+d" or ".%Y+d". - %rpx - Register pair including %X, i.e., {%B|%C, %D|%E, %X, %SP} - %rpy - Register pair including %Y, i.e., {%B|%C, %D|%E, %Y, %SP} III.4. Opcodes The extended opcodes for the Z80 are given below. Those which are underlined are mnemonics which are neither 8080 instructions nor those defined by Zilog for the Z80; they have been invented for CROSS. A complete transliteration from Zilog assembler format to CROSS syntax is given in section III.5. BIT b,opnd z = not .opnd CCD .%A - .MEM[.(%H|%L)]; (%H|%L) = .(%H|%L) - 1; (%B|%C) = .(%B|%C) - 1; {z,s,p} CCDR until .%A eql .MEM[.(%H|%L)] or .(%B|%C) eql 0 do begin .%A - .MEM[.(%H|%L)]; (%H|%L) = .(%H|%L) - 1; (%B|%C) = .(%B|%C) - 1 end; {c,z,p} CCI .%A - .MEM[.(%H|%L)]; (%H|%L) = .(%H|%L) + 1; (%B|%C) = .(%B|%C) - 1; {z,s,p} CCIR until .%A eql .MEM[.(%H|%L)] or .(%B|%C) eql 0 do begin .%A - .MEM[.(%H|%L)]; (%H|%L) = .(%H|%L) + 1; (%B|%C) = .(%B|%C) - 1 end; {c,z,p} CNO CPO; Z80 CROSS-Microcomputer cross assembler 22 CO CPE; DADC %rp (%H|%L) = .(%H|%L) + .%rp + .c; {c,z,n,p} DADX %rpy %X = .%X + .%rpy; {c,n} DADY %rpx %Y = .%Y + .%rpx; {c,n} DJNZ i if .%B @z() 0 then pc = .pc + 2 + i DSBC %rp (%H|%L) = .(%H|%L) - .%rp - .c; n = 1; p = 0; {c,z} EXAF (%A|%PSW) <=> (%A'|%PSW'); EXX (%B|%C) <=> (%B'|%C'); (%D|%E) <=> (%D'|%E'); (%H|%L) <=> (%H'|%L') IM0 im = 0; IM1 im = 1; IM2 im = 2; IND INDR INI INIR INP JMPR i pc = .pc + 2 + i; JNO m JPO m; JO m JPE m; JRC i if .c then JR i; JRNC i if not .c then JR i; JRNZ i if not .z then JR i; JRZ i if .z then JR i; LBCD m (%B|%C) = .MEM[m]; LDAI %A = .iv; LDAR %A = .ra; LDD MEM[.(%D|%E)] = .MEM[.(%H|%L)]; (%D|%E) = .(%D|%E) - 1; (%H|%L) = .(%H|%L) - 1; (%B|%C) = .(%B|%C) - 1; n = 0; LDDR until .(%B|%C) eql 0 do begin MEM[.(%D|%E)] = .MEM[.(%H|%L)]; (%D|%E) = .(%D|%E) - 1; (%H|%L) = .(%H|%L) - 1; (%B|%C) = .(%B|%C) - 1; end; LDED m (%D|%E) = .MEM[m]; LDI .MEM[.(%D|%E)] = .MEM[.(%H|%L)]; (%D|%E) = .(%D|%E) + 1; (%H|%L) = .(%H|%L) + 1; (%B|%C) = .(%B|%C) - 1; {p} LDIR until .(%B|%C) eql 0 do begin MEM[.(%D|%E)] = .MEM[.(%H|%L)]; (%D|%E) = .(%D|%E) + 1; (%H|%L) = .(%H|%L) + 1; (%B|%C) = .(%B|%C) - 1; end; LIXD m %X = .MEM[m+1], .MEM[m]; LIYD m %Y = .MEM[m+1], .MEM[m]; LSPD m %SP = .MEM[m+1], .MEM[m]; NEG %A = - .%A; p = 0; {c,z,s} OUTD OUTDR OUTI OUTIR OUTP PCIX pc = .%X; PCIY pc = .%Y; RALR Z80 CROSS-Microcomputer cross assembler 23 RARR RES b,opnd %opnd = 0; RETI return from interrupt RETN return from nonmaskable interrupt RLCR RLD decimal arithmetic RNO RPO; RO RPE; RRCR RRD decimal arithmetic SBCD m MEM[m] = .(%B|%C); SDED m MEM[m] = .(%D|%E); SET b,opnd opnd = 1; SIXD m MEM[m] = .%X; SIYD m MEM[m] = .%Y; SLAR SPIX %SP = .%X; SPIY %SP = .%Y; SRAR SRLR SSPD m MEM[m] = .%SP; STAI iv = .%A; STAR ra = .%A; XTIX %X <=> MEM[.%SP]; XTIY %Y <=> MEM[.%SP]; III.5. Z80 Transliterations The following transliterations are necessary because of the differences between the Zilog definition of the instructions and the CROSS syntax. This is indexed alphabetically by the Zilog operations in order to facilitate translation of Zilog assembly programs to CROSS. Zilog CROSS ADC i ACI i ADC (HL) ADC M ADC HL,rp DADC %rp ADC (IX+d) ADC d(X) ADC (IY+d) ADC d(Y) ADC r ADC %r ADD i ADI i ADD (HL) ADD M ADD HL,rp DAD %rp ADD (IX+d) ADD d(X) ADD (IY+d) ADD d(Y) ADD r ADD %r AND i ANI i AND (HL) ANA M AND (IX+d) ANA d(X) AND (IY+d) ANA d(Y) AND r ANA %r BIT b,(HL) BIT b,M BIT b,(IX+d) BIT b,d(X) BIT b,(IY+d) BIT b,d(Y) Z80 transliterations CROSS-Microcomputer cross assembler 24 CALL m CALL m CALL C,m CC m CALL M,m CM m CALL NC,m CNC m CALL NZ,m CNZ m CALL NZ,m CNZ m CALL P,m CP m CALL PE,m CPE m CALL PO,m CPO m CALL Z,m CZ m CCF CMC CP i CPI i CP (HL) CMP M CP (IX+d) CMP d(X) CP (IY+d) CMP d(Y) CP r CMP %r CPD CCD CPDR CCDR CPI CCI CPIR CCIR CPL CMA DAA DAA DEC (HL) DCR M DEC IX DCX %X DEC IY DCX %Y DEC (IX+d) DCR d(X) DEC (IY+d) DCR d(Y) DEC rp DCX %rp DEC r DCR %r DI DI DJNZ d DJNZ d EI EI EX AF,AF' EXAF EX DE,HL XCHG EX (SP),HL XTHL EX (SP),IX XTIX EX (SP),IY XTIY EXX EXX HALT HLT IM 0 IM0 IM 1 IM1 IM 2 IM2 IN A,i IN i IN r,(c) INC (HL) INR M INC IX INX %X INC IY INX %Y INC (IX+d) INR d(X) INC (IY+d) INR d(Y) INC rp INX %rp IND IND INDR INDR Z80 transliterations CROSS-Microcomputer cross assembler 25 INI INI INIR INIR JP m JMP m JP M,m JM m JP NC,m JNC m JP NZ,m JNZ m JP NZ,m JNZ m JP P,m JP m JP PE,m JPE m JP PO,m JPO m JP Z,m JZ m JR d JMPR d JR M,m JRM m JR NC,m JRNC m JR NZ,m JRNZ m JR NZ,m JRNZ m JR P,m JRP m JR PE,m JRPE m JR PO,m JRPO m JR Z,m JRZ m LD A,(m) LDA m LD A,(BC) LDAX %B LD A,(DE) LDAX %D LD A,i MVI %A,i LD A,r MOV %A,%r LD (m),A STA m LD (m),BC SBCD m LD (m),DE SDED m LD (m),HL SHLD m LD (m),IX SIXD m LD (m),IY SIYD m LD (m),SP SSPD m LD (BC),A STAX %B LD (DE),A STAX %D LD HL,(m) LHLD m LD (HL),i MVI i LD (HL),r MOV %r,M LD I,A STAI LD IX,(m) LIXD m LD IX,m LXI %X,m LD (IX+d),i MVI i,d(X) LD (IX+d),r MOV %r,d(X) LD IY,(m) LIYD m LD IY,m LXI %Y,m LD (IY+d),i MVI i,d(Y) LD (IY+d),r MOV %r,d(Y) LD r,A MOV %r,%A LD r,i MVI %r,i LD r,(HL) MOV %r,M LD r,(IX+d) MOV %r,d(X) LD r,(IY+d) MOV %r,d(Y) LD r,r MOV %r,%r Z80 transliterations CROSS-Microcomputer cross assembler 26 LD BC,(m) LBCD m LD DE,(m) LDED m LD HL,(m) LHLD m LD SP,(m) LSPD m LD IX,(m) LIXD m LD IY,(m) LIYD m LD rp,m LXI %rp,m LD SP,HL SPHL LD SP,IX SPIX LD SP,IY SPIY LDD LDD LDDR LDDR LDI LDI LDIR LDIR NEG NEG NOP NOP OR i ORI i OR (HL) ORA M OR (IX+d) ORA d(X) OR (IY+d) ORA d(Y) OR r ORA %r OUT (i),r OUT i,A OUT i OUTD OUTD OUTDR OUTDR OUTI OUTI OUTIR OUTIR POP IX POP %X POP IY POP %Y POP rp POP %rp PUSH IX PUSH %X PUSH IY PUSH %Y PUSH rp PUSH %rp RES b,(HL) RES b,M RES b,(IX+d) RES b,d(X) RES b,(IY+d) RES b,d(Y) RES b,r RES b,%r RET RET RET M RM RET NC RNC RET NZ RNZ RET NZ RNZ RET P RP RET PE RPE RET PO RPO RET Z RZ RETI RETI RETN RETN RL (HL) RALR M RL (IX+d) RALR d(X) RL (IY+d) RALR d(Y) RL r RALR %r Z80 transliterations CROSS-Microcomputer cross assembler 27 RLA RAL RLC (HL) RLC M RLC (IX+d) RLC d(X) RLC (IY+d) RLC i(Y) RLC r RLC %r RLCA RLC RLD RLD RR (HL) RARR M RR (IX+d) RARR d(X) RR (IY+d) RARR d(Y) RR r RARR %r RRA RAR RRC (HL) RRC M RRC (IX+d) RRC d(X) RRC (IY+d) RRC d(Y) RRC r RRC %r RRCA RRC RRD RRD RST v RST v SBC i SBI i SBC (HL) SBC M SBC HL,rp DSBC %rp SBC (IX+d) SBC d(X) SBC (IY+d) SBC d(Y) SBC r SBC %r SCF STC SET b,(HL) SET b,M SET b,(IX+d) SET b,d(X) SET b,(IY+d) SET b,d(Y) SET b,r SET b,%r SLA (HL) SLAR M SLA (IX+d) SLAR d(X) SLA (IY+d) SLAR d(Y) SLA r SLAR %r SRA (HL) SRAR M SRA (IX+d) SRAR d(X) SRA (IY+d) SRAR d(Y) SRA r SRAR %r SRL (HL) CB3E SRL (IX+d) DDCBdd3E SRL (IY+d) FDCBdd3E SRL r CB?? SUB i SUI i SUB (HL) SUB M SUB (IX+d) SUB d(X) SUB (IY+d) SUB d(Y) SUB r SUB %r XOR i XRI i XOR (HL) XRA M XOR (IX+d) XRA d(X) XOR (IY+d) XRA d(Y) XOR r XRA %r Z80 transliterations CROSS-Microcomputer cross assembler 28 IV. 8008 The 8008 is described by two different sets of opcodes. The one set is based upon the 8080 style of coding, and is a subset of the operations. The other set is based upon the original set of 8008 mnemonics as described by Intel. Rather than give complete descriptions of these operations, the user is referred back to the 8080 descriptions. What this section will give is a listing of the available operations and a cross reference to the original 8008 mnemonics. Note that the 8008 is "software compatible" with the 8080; the same mnemonics will produce different bit patterns for the 8008 and the 8080. IV.1. 8080 subset The instructions which are implemented for the 8008 are: ACI ADC ADD ADI ANA ANI CALL CC CM CMP CNC CNZ CP CPE CPI CPO CZ DCR HLT IN INR JC JM JMP JNC JNZ JP JPE JPO JZ MOV MVI NOP ORA ORI OUT RAL RAR RC RET RLC RM RNC RNZ RP RPE RPO RRC RST RZ SBB SBI SUB SUI XRA XRI The set of original 8008 operations are defined as: 8080 Original 8008 ADC ACA, ACB, ACC, ACD, ACE, ACH, ACL ACI ACI ADD ADA, ADB, ADC, ADD, ADE, ADH, ADL ADI ADI CALL CAL CNC CFC CPO CFP CM CFS CNZ CFZ CMP CPA, CPB, CPC, CPD, CPE, CPH, CPL CPI CPI CC CTC CPE CTP CP CTS CZ CTZ DCR DCB, DCC, DCD, DCE, DCH, DCL HLT HLT INR INB, INC, IND, INE, INH, INL IN INP JNC JFC JNZ JFZ JPO JFP JM JFS JMP JMP JC JTC JPE JTP 8008 CROSS-Microcomputer cross assembler 29 JP JTS JZ JTZ MOV LAA, LAB, LAC, LAD, LAE, LAH, LAL, LAM, LBA, LBB, LBC, LBD, LBE, LBH, LBL, LBM, LCA, LCB, LCC, LCD, LCE, LCH, LCL, LCM, LDA, LDB, LDC, LDD, LDE, LDH, LDL, LDM, LEA, LEB, LEC, LED, LEE, LEH, LEL, LEM, LHA, LHB, LHC, LHD, LHE, LHH, LHL, LHM, LLA, LLB, LLC, LLD, LLE, LLH, LLL, LLM MVI LAI, LBI, LCI, LDI, LEI, LHI, LLI, LMI ANA NDA, NDB, NDC, NDD, NDE, NDH, NDL, NDM ANI NDI NOP NOP ORA ORA, ORB, ORC, ORD, ORE, ORH, ORL, ORM ORI ORI OUT OUT RAL,RAR RAL, RAR RET RET RNC RFC RPO RFP RP RFS RNZ RFZ RLC,RRC RLC, RRC SUB SBA, SBB, SBC, SBD, SBE, SBH, SBL, SBM SBI SBI SBC SUA, SUB, SUC, SUD, SUE, SUH, SUL, SUM SUI SUI XRA XRA, XRB, XRC, XRD, XRE, XRH, XRL, XRM 8008 CROSS-Microcomputer cross assembler 30 V. 8048 V.1. Machine State - R0-R7 general registers R0 thru R7; R0 and R1 can be used as indirect memory reference registers. - Bus<0,8> Bus register port (latched output, unlatched input) - MB - Temporary location which holds result of last SEL mb. - MEM - Addressible memory - P1<0,8>-P7<0,8> I/O or expansion ports P1 thru P7 - PSW<0,8> Program status word. The following bits in the PSW are named: * SP = PSW<0,3> Stack pointer * RB = PSW<4,1> Register bank select * f1 = PSW<4,1> Software flag F1 (same as RB) * f0 = PSW<5,1> Software flag F0 * ac = PSW<6,1> Auxiliary Carry status bit * c = PSW<7,1> Carry status bit A<0,8> Accumulator - S[0:7]<0,16> Stack - T0 Timer/counter timeout flag; external pin T0 - T1 Counter decrement request; external pin T1 V.2. Notation The operands are: - A - accumulator - acf0f1 - A, c, F0, F1 - addr - 12-bit address specifying a memory byte - ai - analog input 0 or 1 - BUS - bus input-output register - c - carry bit 8048 CROSS-Microcomputer cross assembler 31 - data - 8-bit immediate data - dev - an I/O device - ep - expander port P4, P5, P6 or P7 - F0,F1 - status bits - f - status bits F0 or F1 - I - interrupt signal - TCNTI - timer or interrupt signal - int - I or TCNTI - MB0,MB1 - memory bank select - mb - MB0, MB1 - P1-P7 - I/O or expansion ports - port - I/O port P1 or P2 - R0-R7 - registers R0-R7 - r - register R0 or R1 - @r - memory location MEM[.r] - rn - register R0-R7 - RB0,RB1 - Register bank select - rb - RB0, RB1 - reg - A, R0-R7 - src-opnd - MEM[.r], data or .rn V.3. Syntax Immediate data is expressed as # followed by the data. V.4. Opcodes ADD A,src-opnd A = .A + src-opnd; ADDC A,src-opnd A = .A + src-opnd + .c; ANL port,data port = .port and data; ANL A,src-opnd A = .A and src-opnd; ANL BUS,data Bus = .Bus and data; ANLD ep,A ep = ep and .A<0,4>; CALL addr SP = .SP + 1; Stack[.SP]<0,16> = (.PC<0,8>|.PSW<4,4>|.PC<8,4>); 8048 CROSS-Microcomputer cross assembler 32 PC<11,1> = .MB; PC<0,11> = addr; CLR acf0f1 acf0f1 = 0; CPL acf0f1 acf0f1 = not .acf0f1; DA A DEC reg reg = .reg - 1; DIS int DJNZ rn,addr8 EN int ENT0 CLK Enable timer output on pin T0 IN A,port A = port; INC A,@r MEM[.r] = .MEM[.r] + 1; INS A,BUS A = .Bus; JBn addr8 if .A then PC<0,8> = addr8; JC addr8 if .c then PC<0,8> = addr8; JFf addr8 if .f then PC<0,8> = addr8; JMP addr PC<11,1> = .MB; PC<0,11> = addr; JMPP @A PC<0,8> = .(.PC<8,4>|.A); JNC addr8 if not .c then PC<0,8> = addr8; JNI addr8 if not .i then PC<0,8> = addr8; JNTn addr8 if not .tn then PC<0,8> = addr8; JNZ addr8 if not .z then PC<0,8> = addr8; JTF addr8 JTn if .tn then PC<0,8> = addr8; JZ addr8 if .z then PC<0,8> = addr8; MOV A,@r A = .MEM[.r]; MOV A,T A = .T; MOV @r,A MEM[.r] = .A; MOV @r,data MEM[.reg] = data; MOV reg,data reg = data; MOV A,rn A = .rn; MOV PSW,A PSW = .A; MOV T,A T = .A; MOV rn,A rn = .A; MOVD A,ep A<0,4> = ep; MOVD ep,A ep = .A<0,4>; MOVP A,@A A = .MEM[(.PC<8,4>|.A)]; MOVP3 A,@A A = .MEM[(3|.A)]; MOVX @r,A MEM[.r] = .A; MOVX A,@r A = .MEM[.r]; NOP ; ORL port,data port = .port or data; ORL A,src-opnd A = .A + src-opnd; ORL BUS,data Bus = .Bus or data; ORLD ep,A ep = .ep or .A; OUTL port,A port = .A; OUTL BUS,A Bus = .A; RAD A A = D; RET PC<0,12> = (.Stack[.SP]<0,4>|.Stack[.SP]<8,8>); SP = .SP - 1; RETR PC<0,12> = (.Stack[.SP]<0,4>|.Stack[.SP]<8,8>); PSW<4,4> = .Stack[.SP]<4,4>; SP = .SP -1; RL A A = .A rot 1; RLC A (c|A) = .(c|A) rot 1; 8048 CROSS-Microcomputer cross assembler 33 RR A A = .A rot -1; RRC A (c|A) = .(c|A) rot -1; SEL ai select analog input ai SEL mb MB = mb; SEL rb STOP TCNT Stop counter or timer mode STRT CNT Counter increments on falling edge of T1 STRT T Counter increments every 480 system clock ticks SWAP A .A<0,4> <=> .A<4,4>; XCH A,@r A <=> MEM[.r]; XCH A,rn A <=> rn; XCHD A,@r A<0,4> <=> MEM[.r]<0,4>; XRL A,src-opnd A = .A xor opnd; 8048 CROSS-Microcomputer cross assembler 34 VI. 1802 VI.1. Machine State D The data register DF The "data flag" register, or carry P 4-bit program counter pointer X 4-bit data counter pointer T 8-bit buffer for P and X Q Q-status output register VI.2. Opcodes The operation codes recognized for the 1802 are: ADC D = .mem[.R[.X]] + .D + .DF ADCI D = data8 + .D + .DF ADD D = .mem[.R[.X]] + .D ADI D = data8 + .D AND ANI BDF if .DF then R[P]<7,0> = adr8 BGE BL BM BNF BNQ BNZ BN1 BN2 BN3 BN4 BPZ BQ BR BZ B1 B2 B3 B4 DEC n R[n] = .R[n] - 1; DIS GHI GLO IDL INC n R[n = .R[n] + 1; INP IRX 1802 CROSS-Microcomputer cross assembler 35 LBDF LBNF LBNQ LBNZ LBQ LBR LBZ LDA LDI LDN LDX LDXA LSDF LSIE LSKP LSNF LSNQ LSNZ LSQ LSZ MARK NBR NLBR NOP OR ORI OUT PHI PLO REQ RET RSHL RSHR SAV SD SDB SDBI SDI SEP SEQ SEX SHL SHLC SHR SHRC SKP SM SMB SMBI SMI STR STXD 1802 CROSS-Microcomputer cross assembler 36 XOR XRI 1802 CROSS-Microcomputer cross assembler 37 VII. 6502 VII.1. Machine state The machine state is represented by: - c - The carry bit - z - The zero bit, true if result was zero - v - The overflow bit - s - The sign bit, true if result was negative - d - Decimal mode - i - Interrupt disable bit; 0 => interrupts enabled - b - Breakpoint flag; set by BRK instruction trap The machine registers are: - ac<0,8> - The single accumulator - x<0,8> - index register x, preindexes indirect addresses - y<0,8> - index register y, postindexes indirect addresses. - sp<0,8> - stack pointer. - psw<0,8> - processor status word. VII.2. Notation The operands are expressed as: - opnd8 - 8 bit operand corresponding to one of the form: * addr - Base page direct (8 bit address). * addr,X - Base page indexed by x; MEM[addr + .x]. * (addr,X) - Indexed indirect by x; (.MEM[addr + .x]). * (addr),Y - Indexed indirect by y; (.MEM[addr] + .y). - opnd16 - Any of the following operands in the form: * addr - Extended direct (16 bit address); MEM[addr]. * addr,X - Absolute indexed via x; MEM[addr + .x]. * addr,Y - Absolute indexed via y; MEM[addr + .y]. 6502 CROSS-Microcomputer cross assembler 38 - opnd - Either opnd8 or opnd16. - i - Immediate data, expressed as #expression. VII.3. Syntax The syntax for operands is much like that specified by MOS Technology. Immediate operands are indicated by preceding the operand with a hash mark, #. X- or Y- indexed operands are written as a suffix ",X" or ",Y". VII.4. Opcodes The opcodes recognized for the Mos Technology 6502 are: ADC opnd ac = .ac + .opnd + .c; {s,z,c,v} ADC i ac = .ac + i + .c; {s,z,c,v} AND opnd ac = .ac and .opnd; {s,z} AND i ac = .ac and i; {s,z} ASL opnd c|opnd = opnd lsh 1; {s,z,c} BCC d if not .c then pc = .pc + 1 + d; BCS d if .c then pc = .pc + 1 + d; BEQ d if .z then pc = .pc + 1 + d; BGE d if .c then pc = .pc + 1 + d; Synonym for BCS BIT opnd .ac and .opnd; s = (.ac and .opnd)<7,1>; v = (.ac and .opnd)<6,1>; {z} BLT d if not .c then pc = .pc + 1 + d; Synonym for BCC BMI d if .s then pc = .pc + 1 + d;; BNE d if not .z then pc = .pc + 1 + d;; BPL d if not .s then pc = .pc + 1 + d;; BRK MEM[.sp] = .pc<0,8>; MEM[.sp + 1] = .pc<8,8>; MEM[.sp + 2] = .psw; sp = .sp - 3; pc = $FFFFFFFE; i = 1; b = 1; BVC d if not .v then pc = .pc + 1 + d;; BVS d if .v then pc = .pc + 1 + d;; CLC c = 0; CLD d = 0; CLI i = 0; CLV v = 0; CMP opnd .ac - .opnd; {s,z,c} CPX opnd .x - .opnd; {s,z,c} CPY opnd .y - opnd; {s,z,c} DEC ac = .ac - 1; {s,z} DEX x = .x - 1; {s,z} DEY y = .y - 1; {s,z} EOR opnd ac = .ac - .opnd INC ac = .ac + 1; {z,s} INX x = .x + 1; INY y = .y + 1; JMP m pc = m; JSR m MEM[.sp] = .pc<8,8>; MEM[.sp - 1] = .pc<0,8>; sp = .sp - 2; pc = m; 6502 CROSS-Microcomputer cross assembler 39 LDA opnd ac = .opnd; {s,z} LDX opnd x = .opnd; {s,z} LDY opnd y = .opnd; {s,z} LSR ac|c = .ac|0 lsh -1; NOP ; ORA opnd ac = .ac or opnd; {s,z} PHA MEM[.sp] = .ac; sp = .sp - 1; PHP MEM[.sp] = .psw; sp = .sp - 1; PLA ac = .MEM[.sp + 1]; sp = .sp + 1; PLP psw = .MEM[.sp + 1]; sp = .sp + 1; ROL opnd c|.MEM[opnd] = c|.MEM[opnd] rot 1; {s,z,c} ROR opnd c|.MEM[opnd] = c|.MEM[opnd] rot -1; {s,z,c} RTI psw = .MEM[.sp + 1]; pc<0,8> = .MEM[.sp + 2]; pc<8,8> = .MEM[.sp + 3]; sp = .sp + 3; pc = .pc + 1; RTS pc<0,8> = .MEM[.sp + 1]; pc<8,8> = .MEM[.sp + 2]; sp = .sp + 2; pc = .pc + 1; SBC opnd ac = .ac - .opnd - (not .c); {s,z,c,v} SEC c = 1; SED d = 1; SEI i = 1; STA opnd MEM[opnd] = .ac; {s,z} STX opnd MEM[opnd] = .x; {s,z} STY opnd MEM[opnd] = .y; {s,z} TAX a = .x; TAY a = .y; TSX sp = .x; TXA x = .a; TXS x = .sp; TYA y = .a; 6502 CROSS-Microcomputer cross assembler 40 VIII. 6800 VIII.1. Machine State The registers are: - %A<0,8> - accumulator A - %B<0,8> - accumulator B - %X<0,16> - Index register - sp<0,16> - Stack pointer - pc<0,16> - The program counter The flags are: - c - Carry - o - Overflow - s - Sign - z - Zero - xc - Auxiliary carry VIII.2. Notation - mem - A memory address which can be one of * Base page direct (.MEM[mem], mem 8 bits) * Extended direct (MEM[mem], mem 16 bits) * Indexed (MEM[mem+.%X], mem 8 bits) - memd - A memory address which can be one one of * Extended direct (MEM[memd], memd 16 bits) * Indexed (MEM[memd+.%X], memd 8 bits) - i - An immediate operand, written as #i - i16 - A 16-bit immediate operand, written as #i16 - d - A displacement, usually written as an address; CROSS will compute the actual displacement between the current instruction and the destination address. - opnd - A general operand; may be either mem or i. When interpreted 6800 CROSS-Microcomputer cross assembler 41 as a value, ".opnd" may represent either .MEM[mem] or i. Please excuse the somewhat sloppy notation; it makes the description more compact. - sr - The status register which holds c,z,s,o,xc. VIII.3. Syntax Immediate operands are written with a # symbol, e.g. ADDA #$F9 ; Adds hex F9 to A Indexing is specified by writing ",X" after the operand. The operand must be a value which will fit in 8 bits. foo==$10 ADDA foo,X VIII.4. Opcodes ABA %A = .%A + .%B; {c,z,s,o,xc} ADCA opnd %A = .%A + .opnd + .c; {c,z,s,o,xc} ADCB opnd %B = .%B + .opnd + .c; {c,z,s,o,xc} ADDA opnd %A = .%A + .opnd; {c,z,s,o,xc} ADDB opnd %B = .%b + .opnd; {c,z,s,o,xc} ANDA opnd %A = .%A + .opnd; o=0; {z,s} ANDB opnd %B = .%B + .opnd; o=0; {z,s} ASL memd c=.memd<7,1>; memd=.memd lsh 1; o=.s xor .c; {z,s} ASLA c=.%A<7,1>; %A = .%A lsh 1; o=.s xor .c; {z,s} ASLB c=.%B<7,1>; %B = .%B lsh 1; o=.s xor .c; {z,s} ASR memd c=.memd<0,1>; memd=.memd ash -1; o=.s xor .c; {z,s} ASRA c=.%A<0,1>; %A=.%A ash -1; o=.s xor .c; {z,s} ASRB c=.%B<0,1>; %B=.%B ash -1; o=.s xor .c; {z,s} BCC d if not .c then BRA d; BCS d if .c then BRA d; BEQ d if .z then BRA d; BGE d if not (.o xor .s) then BRA d; BGT d if not (.z or (.s xor .o)) then BRA d; BHI d if not (.c or .z) then BRA d; BHS d if not .c then BRA d; Synonym for BCC BITA mem .%A and .mem; o = 0; {z,s} BITB mem .b and .mem; o = 0; {z,s} BLE d if .z or (.s xor .o) then BRA d; BLO d if .c then BRA d; Synonym for BCS BLS d if .c or .z then BRA d; BLT if .s xor .o then BRA d; BMI d if .s then BRA d; BNE d if not .z then BRA d; BPL d if not .s then BRA d; BR d BRA d; BRA d pc = .pc + 2 + d; BSR d MEM[.sp] = .pc<0,8>; MEM[.sp - 1] = .pc<8,8>; sp = .sp - 2; pc = .pc + d + 2; 6800 CROSS-Microcomputer cross assembler 42 BVC d if not .o then BRA d; BVS d if .o then BRA d; CBA .%A - .%B; {c,z,s,o} CLC c=0; CLI ie = 0; CLR memd memd=0; c=0; z=1; s=0; o=0; CLRA %A = 0; c=0; z=1; s=0; o=0; CLRB %B = 0; c=0; z=1; s=0; o=0; CLV o = 0; CMPA opnd .%A - .opnd; {c,z,s,o} CMPB opnd .%B - .opnd; {c,z,s,o} COM memd memd=~.memd; c=1; o=0; {s,z} COMA %A=~.%A; c=1; o=0; {s,z} COMB %B=~.%B; c=1; o=0; {s,z} CPX memd %X<0,8>-.(memd+1); %X<8,8>-.memd; {s,z,o} DAA decimal arithmetic DEC memd memd=.memd-1; {s,z,o} DECA %A = .%A - 1; {s,z,o} DECB %B = .%B - 1; {s,z,o} DES sp = .sp - 1; DEX %X = .%X - 1; {z} EORA opnd %A=.%A xor .opnd; o=0; {s,z} EORB opnd %B=.%B xor .opnd; o=0; {s,z} INC memd memd=.memd+1; {s,z,o} INCA %A = .%A + 1; {s,z,o} INCB %B = .%B + 1; {s,z,o} INS sp = .sp + 1; INX %x = .%X + 1; {z} JMP mem pc = mem; JSR mem MEM[.sp]=.pc<0,8>; MEM[.sp-1]=.pc<8,8>; sp=.sp-2; pc=mem; LDAAmem A = .mem; o = 0; {o,s,z} LDABmem B = .mem; o = 0; {o,s,z} LDS mem sp<8,8> = .mem; sp<0,8> = .(mem + 1); o = 0; {z,s} LDS i16 sp = i16; {s,z} LDX opnd %X<8,8> = .opnd; %X<0,8> = .(opnd + 1); o = 0; {z,s} LSRA A = .A lsh -1; LSRB B = .B lsh -1; NEG memd memd = 0 -.memd; {c,s,z,o} NEGA %A = 0 - .%A; {c,s,z,o} NEGB %B = 0 - .%B; {c,s,z,o} NOP ; ORAA opnd %A=.%A or .opnd; o=0; {s,z} ORAB opnd %B=.%B or .opnd; o=0; {s,z} PSHA Synonym for PSHS A PSHB Synonym for PSHS B PULA Synonym for PULS A PULB Synonym for PULS B ROL opnd c|opnd = .(c|opnd) rot 1; ROLA c|A = .(c|A) rot 1; ROLB c|B = .(c|B) rot 1; ROR opnd c|opnd = .(c|opnd) rot -1; RORA c|A = .(c|A) rot -1; 6800 CROSS-Microcomputer cross assembler 43 RORB c|B = .(c|B) rot -1; RTI RTS SBA %A = .%A - .%B; {c,z,s,o} SBCA opnd %A = %A - .opnd - .c; {c,z,s,o} SBCB opnd %B = .%B - .opnd - .c; {c,z,s,o} SEC c = 1; SEI ie = 1; SEV o = 1; STAA opnd mem = .%A; STAB opnd mem = .%B; STS mem mem = .sp<8,8>; (mem + 1) = .sp<0,8>; o=0; {s,z} STX mem mem = .%X<8,8>; (mem + 1) = .%X<0,8>; o=0; {s,z} SUBA opnd %A = .%A - .opnd; {c,s,z,o} SUBB opnd %B = .%B - .opnd; {c,s,z,o} SWI software interrupt; TAB %B = .%A; o=0; {s,z} TAP sr = .%A; {c,z,s,o,xc} TBA %A = .%B; o=0; {s,z} TPA %A = .sr TST memd c = 0; z = .memd eql 0; s = .memd < 0; o = 0; TSTA c = 0; z = .%A eql 0; s = .%A < 0; o = 0; TSTB c = 0; z = .%B eql 0; s = .%B < 0; o = 0; TSX %X = .sp + 1; TXS sp = .%X - 1; WAI MEM[.sp]=.pc<0,8>; MEM[.sp-1] = .pc<8,8>; MEM[.sp-2] = .%X<0,8>; MEM[.sp-3] = .%X<8,8>; MEM[.sp-4] = .%A; MEM[.sp-5] = .%B; MEM[.sp-6] = .sr; sp = .sp-7; 6800 CROSS-Microcomputer cross assembler 44 IX. 6805 There is one known bug in the 6805 code. During pass 1, an indexedaddress is assumed to require 2 bytes if it is a forward reference. During pass 2, if CROSS determines that the address can be represented in one byte, it will assign it as one byte. All labels and other position-dependent symbols after this point will now have different values assigned during pass 2; thus generating a phase (P) error. This may be circumvented by explicitly using a > operator to force the address to always be two bytes. IX.1. Machine State A<0,8> Accumulator X<0,8> Index register PC<0,11> Program counter CC<0,5> Condition codes h half-carry (CC<4,1>) i interrupt mask (CC<3,1>) n negative (sign) status (CC<2,1>) z zero status (CC<1,1>) c carry status (CC<0,1>) SP<0,11> Stack pointer; note however that only SP<0,5> is variable; SP<5,6> is constant at ^B000011. il External interrupt line. IX.2. Notation data8 Any immediate 8-bit data. opnd Any operand in the modes direct, extended, indexed (no offset), indexed (8-bit offset), indexed (16-bit offset). opnd8 Any operand in the modes direct, indexed (no offset), or indexed (8-bit offset). label Any operand which can be converted by CROSS to an 8-bit offset (7 bits plus sign). IX.3. Syntax Immediate operands are preceded by #. A > symbol preceding an operand forces that operand to be two bytes. 6805 CROSS-Microcomputer cross assembler 45 A < symbol preceding an operand forces that operand to be one byte. Indexing is indicated by following the operand with (X). IX.4. Opcodes ADC data8 A = .A + data8 + .c; {h,n,z,c} ADC opnd A = .A + .opnd + .c; {h,n,z,c} ADD data8 A = .A + data8; {h,n,z,c} ADD opnd A = .A + .opnd; {h,n,z,c} AND data8 A = .A and data8; {n,z} AND opnd A = .A and .opnd; {n,z} ASL opnd8 opnd8 = .opnd8 ash 1; {n,z,c} ASLA A = .A ash 1; {n,z,c} ASLX X = .X ash 1; {n,z,c} ASR opnd8 opnd8 = .opnd8 ash -1; {n,z,c} ASRA A = .A ash -1; {n,z,c} ASRX X = .X ash -1; {n,z,c} BCC label if not .c then BRA label; BCLRn opnd8 opnd8 = 0; BCS label if .c then BRA label; BEQ label BHCC label if not .h then BRA label; BHCS label if .h then BRA label; BHI label BHS label if not .c then BRA label; BIH label if .il then BRA label; BIL label if not .il then BRA label; BIT label {n,z} BLO label if .c then BRA label; BLS label BMC label if not .i then BRA label; BMS label if .i then BRA label; BNE label if not .z then BRA label; BPL label if not .n then BRA label; BRA label PC = .PC + signextended(label); BRN label ; BRCLR opnd8,label BRSET opnd8,label BSETn opnd opnd = 1; CLC c = 0; {c} CLI i = 0; {i} CLR opnd8 opnd8 = 0; n = 0; z = 1; {n,z} CLRA A = 0; n = 0; z = 1; {n,z} CLRX X = 0; n = 0; z = 1; {n,z} CMP data .A - data; {n,z,c} CMP opnd .A - .opnd; {n,z,c} COM opnd8 opnd8 = not .opnd8; c = 1; {n,z,c} COMA A = not .A; c = 1; {n,z,c} COMX X = not .X; c = 1; {n,z,c} CPX data .X - data; {n,z,c} CPX opnd .X - .opnd; {n,z,c} 6805 CROSS-Microcomputer cross assembler 46 DEC opnd8 opnd8 = .opnd8 - 1 ; {n,z} DECA A = .A - 1; {n,z} DECX X = .X - 1; {n,z} INC opnd8 opnd8 = .opnd8 + 1 ; {n,z} INCA A = .A + 1; {n,z} INCX X = .X + 1; {n,z} JMP opnd JSR opnd LDA data A = data; {n,z} LDA opnd A = .opnd; {n,z} LDX data X = data; {n,z} LDX opnd X = .opnd; {n,z} LSL opnd8 opnd8 = .opnd8 lsh 1; {n,z,c} LSLA A = .A lsh 1; {n,z,c} LSLX X = .X lsh 1; {n,z,c} LSR opnd8 opnd8 = .opnd8 lsh -1; n = 0; {n,z,c} LSRA A = .A lsh -1; n = 0; {n,z,c} LSRX X = .X lsh -1; n = 0; {n,z,c} NEG opnd8 opnd8 = -.opnd8; {n,z,c} NEGA A = -.A; {n,z,c} NEGX X = -.X; {n,z,c} NOP ; ORA data A = .A or data; {n,z} ORA opnd A = .A or .opnd; {n,z} ROL opnd8 (c|opnd8) = .(c|opnd8) rot 1; {n,z,c} ROLA (c|A) = .(c|A) rot 1; {n,z,c} ROLX (c|X) = .(c|X) rot 1; {n,z,c} ROR opnd8 (c|opnd8) = .(c|opnd8) rot -1; {n,z,c} RORA (c|A) = .(c|A) rot -1; {n,z,c} RORX (c|X) = .(c|X) rot -1; {n,z,c} RSP RTI RTS SBC data A = .A - data - .c; {n,z,c} SBC opnd A = .A - .opnd; {n,z,c} SEC c = 1; {c} SEI i = 1; {i} STA opnd opnd = .A; {n,z} STOP STX opnd opnd = .X; {n,z} SUB data A = .A - data; {n,z,c} SUB opnd A = .A - .opnd; {n,z,c} SWI TAX X = .A; TST opnd8 .opnd8 - 0; {n,z} TXA A = .X; 6805 CROSS-Microcomputer cross assembler 47 X. 6809 There is one known bug in the 6809 code. During pass 1, a PC-relativeaddress is assumed to require 2 bytes if it is a forward reference. During pass 2, if CROSS determines that the address can be represented in one byte because it is less than 256 locations ahead, it will assign it as one byte. All labels and other position-dependent symbols after this point will now have different values assigned during pass 2; thus generating a Phase (P) error. This may be circumvented by explicitly using a > operator to force the address to always be two bytes. X.1. Machine State A<0,8> Accumulator A B<0,8> Accumulator B CC<0,8> Condition codes e "entire" flag - indicates action on RTI instruction f FIRQ interrupt request mask; 1 => disabled h Aux carry (half carry); BCD arithmetic i IRQ interrupt request mask; 1 => disabled s Sign bit (1 => negative) z Zero bit (1 => zero result) v Overflow bit c Carry bit D<0,16> A|B DP<0,8> Direct page register PC<0,16> program counter S<0,16> stack pointer register U<0,16> stack pointer register X<0,16> index register Y<0,16> index register 6809 CROSS-Microcomputer cross assembler 48 X.2. Notation - addr - any of the permissible addressing modes, direct page, one byte, two byte, indexed, indirect, etc. - opnd8 - any one-byte operand, except immediate - opnd16 - any two-byte operand, except immediate - data8 - 8 bit immediate data - data16 - 16 bit immediate data - reglist - A list of register names from the set CC, A, B, DP, X, Y, U or S, PC X.3. Syntax - A - accumulator A - B - accumulator B - CC - condition codes - D - accumulator D (=A|B) - DP - direct page register DP - PC - Program counter - PCR - Program counter relative addressing - S - Stack pointer S - U - Stack pointer U - X - Index register X - Y - Index register Y Binary values are indicated by preceding the value with a % symbol. Immediate operands are written with a # in front of the expression; the value of the operand or an explicit size specification, either with < or >, determines if it is a data8 or data16. Those instructions which require double-width immediate operands will force data16 values even if the value will normally fit in a single byte. An explicit one-byte address or operand, opnd8, is designated by a < symbol. An explicit two-byte address or operand, opnd16, is designated by a > symbol. 6809 CROSS-Microcomputer cross assembler 49 Indirect operands are enclosed in [] symbols; an indirect operand can be a one-byte or two-byte operand. Indexed, autoincrement, and autodecrement modes are permitted. Indexing is indicated by suffixing a ",r" to the operand, for various values of index registers (X, Y, S, U, PC, PCR). Single auto-decrement of register operands is indicated by prefixing a single - symbol; double auto-decrement by two such symbols: --. Single auto-increment of register operands is indicated by suffixing a single + symbol; double auto-increment by two such symbols: ++. Note that the form which omits the comma before the register in indexed modes, which is used in the 6809 assembler, is not accepted by CROSS, e.g., 6809 CROSS R+ ,R+ -R ,-R R ,R [R] [,R] R >,R >[R] >[,R] X.4. Opcodes .SETDP addr Indicates to the assembler that the direct page register refers to addr; any references to that page will be handled as direct page references. ABX X = .X + .B; Unsigned add ADCA opnd A = .A + .opnd + .c; {h,n,z,v,c} ADCA data A = .A + data + .c; {h,n,z,v,c} ADCB opnd B = .B + .opnd + .c; {h,n,z,v,c} ADCB data B = .B + data + .c; {h,n,z,v,c} ADDA opnd A = .A + .opnd; {h,n,z,v,c} ADDA data A = .A + data; {h,n,z,v,c} ADDB opnd B = .B + opnd; {h,n,z,v,c} ADDB data B = .B + data; {h,n,z,v,c} ADDD opnd (A|B) = .(A|B) + .opnd; {n,z,v,c} ADDD data (A|B) = .(A|B) + data; {n,z,v,c} ANDA opnd A = .A and .opnd; v = 0; {n,z,v} ANDA data A = .A and data; v = 0; {n,z,v} ANDB opnd B = .B and opnd; v = 0; {n,z,v} ANDA data B = .B and data; v = 0; {n,z,v} ANDCC data8 CC = .CC and data8; {f,h,i,n,z,v,c} ASL opnd opnd = .opnd ash 1; {h,n,z,v,c} ASLA A = .A ash 1; {h,n,z,v,c} ASLB B = .B ash 1; {h,n,z,v,c} ASR opnd opnd = .opnd ash -1; {h,n,z,v,c} ASRA A = .A ash -1; {h,n,z,v,c} 6809 CROSS-Microcomputer cross assembler 50 ASRB B = .B ash -1; {h,n,z,v,c} BCC opnd if not .c then BRA opnd; BCS opnd if .c then BRA opnd; BEQ opnd if .z then BRA opnd; BGE opnd if not (.n xor .v) then BRA opnd BGT opnd if not (.z or (.n xor .v)) then BRA opnd BHI opnd if not (.c xor .z) then BRA opnd BHS opnd if not .c then BRA opnd BITA .A and opnd; v = 0; {n,z,v} BITB .B and opnd; v = 0; {n,z,v} BLE opnd if .z or (.n xor .v) then BRA opnd BLO opnd if .c then BRA opnd BLS opnd if (.c or .z) then BRA opnd BLT opnd if (.n xor .v) then BRA opnd BMI opnd if .n then BRA opnd BNE opnd if not .z then BRA opnd BPL opnd if not .n then BRA opnd BR BRA BRN ; BSR BVC opnd if not .v then BRA opnd; BVS opnd if .v then BRA opnd; CLR opnd opnd = 0; n = 0; z = 1; v = 0; c = 0; {n,z,v,c} CLRA A = 0; n = 0; z = 1; v = 0; c = 0; {n,z,v,c} CLRB B = 0; n = 0; z = 1; v = 0; c = 0; {n,z,v,c} CMPA opnd .A - .opnd; {h,n,z,v,c} CMPB opnd .B - .opnd; {h,n,z,v,c} CMPB data .B - data; {h,n,z,v,c} CMPD opnd .(A|B) - .opnd; {h,n,z,v,c} CMPD data .(A|B) - data; {h,n,z,v,c} CMPS opnd .S - .opnd; {n,z,v,c} CMPS data .S - data; {h,n,z,v,c} CMPU opnd .U - .opnd; {n,z,v,c} CMPU data .U - data; {h,n,z,v,c} CMPX opnd .X - .opnd; {n,z,v,c} CMPX data .X - data; {h,n,z,v,c} CMPY opnd .Y - .opnd; {n,z,v,c} CMPY data .Y - data; {h,n,z,v,c} COM opnd opnd = not .opnd; v = 0; c = 1; {n,z,v,c} COMA A = not .A; v = 0; c = 1; {n,z,v,c} COMB B = not .B; v = 0; c = 1; {n,z,v,c} CPX CWAI data8 e = 1; PSHS PC,U,Y,X,DP,B,A,CC; .CC and data8;} wait for interrupt {f,h,i,n,z,v,c} DAA bcd arithmetic adjust {n,z,v,c} DEC opnd opnd = .opnd -1; {n,z,v} DECA A = .A - 1; {n,z,v} DECB B = .B - 1; {n,z,v} EORA opnd A = .A xor .opnd; v = 0; {n,z,v} EORA data A = .A xor data; v = 0; {n,z,v} EORB opnd B = .B xor .opnd; v = 0; {n,z,v} 6809 CROSS-Microcomputer cross assembler 51 EORB data B = .B xor data; v = 0; {n,z,v} EXG r ,r r <=> r ; {h,f,i,n,z,v,c} 1 2 1 2 INC opnd opnd = .opnd + 1; {n,z,v} INCA A = .A + 1; {n,z,v} INCB B = .B + 1; {n,z,v} JMP opnd PC = opnd; JSR LBCC opnd if not .c then LBRA opnd; LBCS opnd if .c then LBRA opnd; LBEQ opnd if .z then LBRA opnd; LBGE opnd if not (.n xor .v) then LBRA opnd; LBGT opnd if not (.z or (.n xor .v)) then LBRA opnd; LBHI opnd if not (.c xor .z) then LBRA opnd; LBHS opnd if not .c then LBRA opnd; LBLE opnd if .z or (.n xor .v) then LBRA opnd; LBLO opnd if .c then LBRA opnd; LBLS opnd if (.c or .z) then LBRA opnd; LBLT opnd if (.n xor .v) then LBRA opnd; LBMI opnd if .n then LBRA opnd; LBNE opnd if not .z then LBRA opnd; LBPL opnd if not .n then LBRA opnd; LBR LBRA LBRN ; LBSR LBVC opnd if not .v then LBRA opnd; LBVS opnd if .v then LBRA opnd; LDA opnd A = .opnd; v = 0; {n,z,v} LDA data A = data; v = 0; {n,z,v} LDAA Synonym for LDA LDAB Synonym for LDB LDB opnd B = .opnd; v = 0; {n,z,v} LDB data B = data; v = 0; {n,z,v} LDD opnd (A|B) = (.opnd|.(opnd+1)); v = 0; {n,z,v} LDD data16 (A|B) = data16; v = 0; {n,z,v} LDS opnd S = (.opnd|.(opnd+1)); v = 0; {n,z,v} LDS data16 S = data16; v = 0; {n,z,v} LDU opnd U = (.opnd|.(opnd+1)); v = 0; {n,z,v} LDU data16 U = data16; v = 0; {n,z,v} LDX opnd X = (.opnd|.(opnd+1)); v = 0; {n,z,v} LDX data16 X = data16; v = 0; {n,z,v} LDY opnd Y = (.opnd|.(opnd+1)); v = 0; {n,z,v} LDY data16 Y = data16; v = 0; {n,z,v} LEAS opnd S = opnd; LEAU opnd U = opnd; LEAX opnd X = opnd; {z} LEAY opnd Y = opnd; {z} LSL opnd opnd = .opnd lsh 1; {h,n,z,v,c} LSLA A = .A lsh 1; {h,n,z,v,c} LSLB B = .B lsh 1; {h,n,z,v,c} LSR opnd opnd = .opnd lsh -1; n = 0; {n,z,c} 6809 CROSS-Microcomputer cross assembler 52 LSRA A = .A lsh -1; n = 0; {n,z,c} LSRB B = .B lsh -1; n = 0; {n,z,c} MUL (A|B) = .A * .B; {z,c} NEG opnd opnd = - .opnd; {h,n,z,v,c} NEGA A = - .A; {h,n,z,v,c} NEGB B = - .B; {h,n,z,v,c} NOP ; ORA opnd A = .A or .opnd; v = 0; {n,z,v} ORA data A = .A or data; v = 0; {n,z,v} ORAA opnd Synonym for ORA ORAB opnd Synonym for ORB ORB opnd B = .B or .opnd; v = 0; {n,z,v} ORB data B = .B or data; v = 0; {n,z,v} ORCC data8 CC = .CC or data8; {f,h,i,n,z,v,c} PSHS reglist if PC in reglist then (S=.S-1; .S = .PC<0,8>; S=.S-1; .S=.PC<8,8>); if U in reglist then (S=.S-1; .S = .U<0,8>; S=.S-1; .S=.U<8,8>); if Y in reglist then (S=.S-1; .S = .Y<0,8>; S=.S-1; .S=.Y<8,8>); if X in reglist then (S=.S-1; .S = .X<0,8>; S=.S-1; .S=.X<8,8>); if DP in reglist then (S=.S-1; .S = .DP;) if B in reglist then (S=.S-1; .S = .B<0,8>;) if A in reglist then (S=.S-1; .S = .A;) if CC in reglist then (S=.S-1; .S = .CC;) PSHU reglist if PC in reglist then (U=.U-1; .U = .PC<0,8>; U=.U-1; .U=.PC<8,8>); if S in reglist then (U=.U-1; .U = .S<0,8>; U=.U-1; .U=.S<8,8>); if Y in reglist then (U=.U-1; .U = .Y<0,8>; U=.U-1; .U=.Y<8,8>); if X in reglist then (U=.U-1; .U = .X<0,8>; U=.U-1; .U=.X<8,8>); if DP in reglist then (U=.U-1; .U = .DP;) if B in reglist then (U=.U-1; .U = .B<0,8>;) if A in reglist then (U=.U-1; .U = .A;) if CC in reglist then (U=.U-1; .U = .CC;) PULS reglist if CC in reglist then (CC = .(.S); S=.S+1); if A in reglist then (A = .(.S); S=.S+1); if B in reglist then (B = .(.S); S=.S+1); if DP in reglist then (DP = .(.S); S=.S+1); if X in reglist then (X<8,8> = .(.S); S=.S+1; X<0,8> = .(.S); S=.S+1); if Y in reglist then (Y<8,8> = .(.S); S=.S+1; Y<0,8> = .(.S); S=.S+1); if U in reglist then (U<8,8> = .(.S); S=.S+1; U<0,8> = .(.S); S=.S+1); if PC in reglist then (PC<8,8>= .(.S); S=.S+1; PC<0,8> = .(.S); S=.S+1); PULU reglist if CC in reglist then (CC = .(.U); U=.U+1); if A in reglist then (A = .(.U); U=.U+1); 6809 CROSS-Microcomputer cross assembler 53 if B in reglist then (B = .(.U); U=.U+1); if DP in reglist then (DP = .(.U); U=.U+1); if X in reglist then (X<8,8> = .(.U); U=.U+1; X<0,8> = .(.U); U=.U+1); if Y in reglist then (Y<8,8> = .(.U); U=.U+1; Y<0,8> = .(.U); U=.U+1); if S in reglist then (S<8,8> = .(.U); U=.U+1; S<0,8> = .(.U); U=.U+1); if PC in reglist then (PC<8,8>= .(.U); U=.U+1; PC<0,8> = .(.U); S=.S+1); ROL opnd c|opnd = .(c|opnd) rot 1; ROLA c|A = .(c|A) rot 1; ROLB c|B = .(c|B) rot 1; ROR opnd c|opnd = .(c|opnd) rot 1; RORA c|A = .(c|A) rot -1; RORB c|B = .(c|B) rot -1; RTI RTS SBCA opnd A = .A - .opnd - .C; {n,z,v,c} SBCA data A = .A - data - .C; {n,z,v,c} SBCB opnd B = .B - .opnd - .C; {n,z,v,c} SBCB data B = .B - data - .C; {n,z,v,c} SEX sign extend B into A; v = 0; {n,z,v} STA opnd opnd = .A; v = 0; {n,z,v} STAA opnd Synonym for STA STAB opnd Synonym for STB STB opnd opnd = .B; v = 0; {n,z,v} STD opnd opnd|opnd+1 = .(A|B); v = 0; {n,z,v} STS opnd opnd|opnd+1 = .S; v = 0; {n,z,v} STU opnd opnd|opnd+1 = .U; v = 0; {n,z,v} STX opnd opnd|opnd+1 = .X; v = 0; {n,z,v} STY opnd opnd|opnd+1 = .Y; v = 0; {n,z,v} SUBA opnd A = .A - .opnd; {n,z,v,c} SUBA data A = .A - data; {n,z,v,c} SUBB opnd B = .B - .opnd; {n,z,v,c} SUBB data B = .B - data; {n,z,v,c} SUBD opnd (A|B) = .(A|B) - .opnd|.(opnd+1); {n,z,v,c} SUBD data (A|B) = .(A|B) - data; {n,z,v,c} SWI software interrupt PSHS PC,U,Y,X,DP,B,A,CC; e=1; i=1; f=1; PC = ^HFFFA; SWI2 software interrupt PSHS PC,U,Y,X,DP,B,A,CC; e=1; i=1; f=1; PC = ^HFFF4; SWI3 software interrupt PSHS PC,U,Y,X,DP,B,A,CC; e=1; i=1; f=1; PC = ^HFFF2; SYNC synchronize TFR r ,r r = r 1 2 2 1 TST opnd .opnd - 0; v = 0; {n,z,v} TSTA .A - 0; v = 0; {n,z,v} TSTB .B - 0; v = 0; {n,z,v} 6809 CROSS-Microcomputer cross assembler 54 XI. Compiler directives The following compiler directives and their presumed meanings are described briefly here. This is only a refresher for those who have read the DEC assembler description. .ABS Compile non-relocatable (absolute) code. .ADDR Generates a 16-bit address with the bytes in swapped order, i.e., . Equivalent of a compile-time byte-swap operation on a .WORD. .ASCII ASCII string delimited by paired markers. .ASCIZ ASCIZ string delimited by paired markers and supplied with terminal null byte. .ASECT Not implemented in CROSS. .BLKB Allocate space for a number of bytes as specified by the operand. .BLKW Allocate space for a number of words as specified by the operand. .BYTE Each expression supplied will be stored in a single byte. .CSECT Not implemented in CROSS. .DEPHA Dephase; leave .PHASE control area. .DSABL See chapter 5. .ENABL See chapter 5. .END End of program. .ENDC End of conditional; paired with .IF. .ENDM End of macro definition or repeat; paired with .MACRO, .IRP, .IRPC, .REPT. .ENDR End of repetition; paired with .REPT; equivalent to .ENDM in this context. .EOT End-of-tape; assembler will wait for next tape to be loaded (paper tape hackers only). .EQUIV Equates two symbols: .equiv defsym,anysym The symbols may be user symbols, builtin symbols, or macros. Compiler directives CROSS-Microcomputer cross assembler 55 .ERROR Causes an error message to be issued. The optional expression is evaluated and output if present. label: .Print expr;text .FLT2 ? .FLT4 ? .GLOBL Not implemented in CROSS. .IF Enter a conditional. .IFDF .IFDF true if symbol is defined. See also .IFNDF. .IFEQ .IFEQ true if expression evaluates to zero. .IFF Begins body of conditional if enclosing condition was false. .IFG .IFG true if expression greater than zero. .IFGE .IFGE true if expression greater than or equal to zero. .IFGT Same as .IFG .IFL .IFL true if expression is negative. .IFLE .IFLE true if expression is negative or zero. .IFLT Same as .IFL. .IFNDF .IFNDF true if symbol is undefined. .IFNE .IFNE true if expression is non-zero. .IFNZ Same as .IFNE .IFT Begins body of conditional if enclosing condition was true. .IFTF Text from here to the next .IFT, .IFF or .IFTF or the end of the conditional will be included independent of the value of the condition of the enclosing conditional. .IFZ Same as .IFE .IIF condition, arg, stmnt Immediate if; if condition is met, stmnt is emitted. .IRP Indefinite repeat of the body; Sucessive arguments from arglist are assigned to sym. Compiler directives CROSS-Microcomputer cross assembler 56 .IRP sym,arglist body .ENDR .IRPC Indefinite repeat of the body. Successive characters of string are assigned to sym. .IRPC sym,string body .ENDR .LIMIT Not implemented in CROSS. .LIST Enable listing. .LOCAL Not implemented in CROSS. .MACRO Begin a macro definition .MACRO name arglist body .ENDM .MCALL Call macros from the system library. See chapter 7. .MEXIT Leave macro expansion .NARG sym The symbol is equated to the number of arguments to the macro .NCHR sym,str The symbol sym is equated to the number of characters in the delimited string str .NLIST Turn off listing .NTYPE sym,arg The symbol is equated to the addressing mode of the argument. .PAGE Force a page break .PDP10 Irrelevant .PHASE Assemble code as if it were located according to the argument of this directive. .PRINT Print the text which follows on the terminal. label: .Print expr;text .PSECT Not implemented in CROSS. .RADIX Change the radix to the value specified to this directive. Compiler directives CROSS-Microcomputer cross assembler 57 .RAD50 Each argument is converted to a radix50 representation, according to the PDP-11 radix50 conventions. This allows packing three bytes of compressed data in a 16-bit word. (The "50" is octal 50) .REM Include a remark .REPT (.REPT ) Repeat the body of this directive the indicated number of times. .ROUND Perform arithmetic operations with rounding to integer result (see also .TRUNC). .SBTTL Specify subtitle text. .SETDP (6809 only) Tells the assembler which page is currently being addressed by the Direct Page register; see page 49. .TITLE Specify title text. .TRUNC Perform arithmetic operations with truncation to integer result (see also .ROUND) .WORD Allocate space for each value specified. Each expression evaluates to a word (16 bits). Compiler directives CROSS-Microcomputer cross assembler 58 XII. Macro quick summary ? When specified with a formal, will cause a compiler-generated symbol to be provided if an actual is not given in that position. ' Internal concatenation character \ When used as an argument, evaluates before performing the actual-formal match. Macro summary CROSS-Microcomputer cross assembler 59 XIII. Assembler syntax quick summary <...> Encloses any expression (the assembler's equivalent of parentheses). Expressions are evaluated left-to-right without operator heirarchy. + Addition or unary plus - Subtraction or unary minus * Multiplication / Division & Logical and ! Logical or ; Begins comment field ' Indicates single ASCII character as a term in expressions. @ Indicates octal radix number; same as ^O prefix (not valid in 8048 mode, where it is used to indicate addressing modes). ^B Indicates binary number ^C Takes the unary complement ("not") of the following expression ^H Indicates hexadecimal number ^O Indicates octal number = Symbol assignment . Current location counter $ Indicates hexadecimal number % Indicates binary number (6502/6800/6805/6809 mode only) ^ If a postfix operator, divides the expression by 256. \ If a postfix operator, takes the evaluated expression modulo 256 (low byte). Assembler summary CROSS-Microcomputer cross assembler 60 XIV. Error codes A Addressing error; illegal mode, length of address, signed offset, etc. D Doubly-defined symbol referenced. E .end directive not found (its presence is assumed). I Illegal character detected, i.e., a non-printing character; printed as ? in the listing file. L Line buffer overflow; input line too long. M Multiple definition of a label; remember that labels are unique only to the first 6 characters. N Number error; a digit not legal in the given radix has appeared. O Opcode or directive error. P Phase error; a label has a different value between pass 1 and pass 2. Possible causes are strange conditional expansions, phase conditionals, etc. but note also that some modes which generate "short" and "long" addresses may generate different lengths on different passes. See the warnings on pages 44 and 47. Q Questionable syntax. There are missing instructions, or the instruction scan was not completed, or a comment was not properly delimited. R Register error; improper use of a register operand. T Truncation error; a value has more than 16 bits of significance in a 16-bit context or more than 8 bits of significance in an 8-bit context. U Undefined symbol. The undefined symbol is assigned a value of 0. Z Instruction error. The instruction flagged may not be available on the destination processor. This warning occurs when z-80 instructions are used without a .enable z80 directive. Assembler summary CROSS-Microcomputer cross assembler 61 XV. Object format XV.1. PTP object format If the /PTP switch is given (and it must be given with the output file name, not as part of the input file specification), the object format is an ASCII file. The details are determined by either the default output format derived from the input file extension, or by the argument to the /PTP switch; see page 5. XV.1.1. COSMAC format XV.1.2. INT Format This format is used by Intel, Mostek, and the CP/M operating system. Leader: One character, a colon, indicating the start of a record. All characters preceding the colon should be ignored. Byte count: Two characters (ASCII-encoded hex) indicating the number of data bytes in the record. This byte count does not include the leader character, byte count, or address information. Each data byte is represent by two characters, this is not a character count. Address: Four characters (ASCII-encoded hex) indicating the starting load address for the record. Record Type: Two characters, always 00, meaning an absolute block. This is 00 even in blocks that contain just a starting address. The starting address should be detected by a data length of 0, rather than the record type. In this format, the starting address is often given with record type 01. CROSS does not do this. Data: Several pairs of ASCII-encoded hex bytes to be loaded. Checksum: Two characters of (ASCII-encoded hex) checksum. The checksum is the negated 8-bit sum of the byte count, address high, address low, and data bytes, after they have been converted to binary. XV.1.3. KIM Format Leader: One character, a semi-colon, indicating the start of a record. All characters preceding the semi-colon should be ignored. Byte count: Two characters (ASCII-encoded hex) indicating the number of Object format CROSS-Microcomputer cross assembler 62 data bytes in the record. This byte count does not include the leader character, byte count, or address information. Each data byte is represent by two characters, this is not a character count. Address: Four characters (ASCII-encoded hex) indicating the starting load address for the record. Data: Several pairs of ASCII-encoded hex bytes to be loaded. Checksum: Four characters of (ASCII-encoded hex) checksum. The checksum is the negated 16-bit sum of the byte count, address high, address low, and data bytes, after they have been converted to binary. XV.1.4. MOT Format This format uses the S1 and S9 records of the standard Motorola format. The S1 record is a data record, and consists of: S1 The characters which indicate the record type. Byte count Two characters of byte count (ASCII-encoded hex); the byte count is the count of all following data bytes, including the checksum. Address Four characters (ASCII-encoded hex) indicated the starting load address for the record. Data Two characters of ASCII-encoded hex for each byte to be loaded. Checksum A two character (one byte, ASCII-encoded hex) checksum of the binary values of the byte count, address, and data bytes. The sum of all these bytes plus the checksum should equal FF . 16 An S9 record is a transfer record, and consists of: S9 The record type indicator Byte count Same as an S1 record. Address Four characters (two bytes ASCII-encoded hex); the transfer address at which exection should begin; if there was no address on the .end statement, the value 0 is assumed. Checksum Same as an S1 record. XV.2. Binary file formats Object format CROSS-Microcomputer cross assembler 63 XV.2.1. Packed binary file format +---+---------------+---------------+---+---------------+---------------+ |///| byte 2 | byte 1 |///| byte 4 | byte 3 | |///| | |///| | | +---+---------------+---------------+---+---------------+---------------+ 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 2 This is the "packed" output mode . The bytes must first be serialized, and then interpreted according to the description given in section XV.2.3. XV.2.2. Image binary file format The image binary output form consists of one 8-bit byte in the low-order 8 bits of a PDP-10 word. Word 0 of the output file is the first byte, word 1 of the output file is the second byte, etc. The bytes must be interpreted according to the description given in section XV.2.3. XV.2.3. Object format After obtaining a serial byte stream from either a packed or image binary file, the bytes are interpreted as: - some number (zero or more) of 0 bytes (discard) - a byte with the value 1. (This byte is counted in the checksum). - a byte with the value 0. (This byte is counted in the checksum, but of course it has no effect because it is 0). - The low-order 8 bits of the byte count, which we will refer to as BC . L - The high-order 8 bits of the byte count, which we will refer to as BC . The byte count BC is thus computed by H BC = (BC * 400 ) + BC H 8 L 2 If you stare at this and squint your eyes a bit, you will see that it is laid down as two PDP-11 words; the first word is in the left PDP-10 halfword, so the lower-addressed byte is to the right. The second word is in the right PDP-10 halfword. Object format CROSS-Microcomputer cross assembler 64 - The low-order 8 bits of the address where the data will go, which we will refer to as A . This byte is counted as part of BC. L - The high-order 8 bits of the address where the data will go, which we will refer to as A . This byte is counted as part of BC. The load H address A is computed as the byte count, i.e., A = (A * 400 ) + A H 8 L - BC-6 bytes of data, in order, starting with the byte for the address A, then A+1, A+2, etc. - One byte of checksum, which is the complemented sum of all the bytes. When all of the bytes starting at the constant 1 plus the checksum are added, the result should be zero. The above is repeated as often as required to load the data. The last such group has BC=6 and the starting address is A. Thus, it contains no data bytes. This is the only way to distinguish this "transfer address" record from any other record. Object format CROSS-Microcomputer cross assembler 65 XVI. Site-specific differences The CROSS program can be configured for various sites. It is suggested that if you wish to make site-specific changes, you make them in a copy of the master copy of the source, which currently resides at @Rutgers. Use conditional compilation switches, and when you are done, contact Rutgers to take your source back. In this way, we have the advantage of shared maintenance. Please contact Joe Newcomer (Newcomer@CMU-10A) for up-to-date documentation sources. The current site-dependent configuration switches are: CMUASW Uses CMU PPN format for CMU TOPS-10 systems CMUSW Looks for SWITCH.INI on device HOM: first. Sets default page length and width for the Dover printer using SAILA8. UTAHSW Uses [4,156], , as the PPN for .MCALL libraries. Object format CROSS-Microcomputer cross assembler 66 Index ! 59 #, in cref 9 $ 1, 59 % 1, 59 %nn, register 1 & 59 ', concatenation 58, 59 * 59 *, in cref 9 + 59 - 59 ., location counter 59 .ABS 54 .ADDR 54 .ASCII 54 .ASCIZ 54 .ASECT 54 .BLKB 54 .BLKW 54 .BYTE 54 .CSECT 54 .DEPHAse 54 .DSABL 5, 12, 54 .ENABL 4, 12, 54 .END 54 .ENDC 54 .ENDM 54 .ENDR 54 .EOT 54 .EQUIV 54 .ERROR 54 .FLT2 55 .FLT4 55 .GLOBL 55 .IF 55 .IFDF 55 .IFEQ 55 .IFF 55 .IFG 55 .IFGE 55 .IFGT 55 Index CROSS-Microcomputer cross assembler 67 .IFL 55 .IFLE 55 .IFLT 55 .IFNDF 55 .IFNE 55 .IFNZ 55 .IFT 55 .IFTF 55 .IFZ 55 .IIF 55 .IRP 55 .IRPC 56 .LIMIT 56 .LIST 4, 7, 8, 56 .LOCAL 56 .MACRO 56 .MCALL 14, 56 .MEXIT 56 .NARG 56 .NCHR 56 .NLIST 4, 7, 8, 56 .NTYPE 56 .PAGE 56 .PDP10 56 .PHASE 56 .PRINT 56 .PSECT 56 .RAD50 56 .RADIX 56 .REM 57 .REPT 57 .ROUND 12, 57 .SBTTL 57 .SETDP 49, 57 .TITLE 57 .TRUNC 12, 57 .WORD 57 / 59 /CDR 5 /CRF 5, 9 /DS 5, 12 /EN 4, 12 /EQ 6 /GNS 6, 10 /I 5 /LEN 6, 10 /LI 4, 8 /M05 4 /M08 4 /M18 4 /M48 4 Index CROSS-Microcomputer cross assembler 68 /M65 4 /M68 4 /M69 4 /M80 4 /M88 4 /MF8 4 /N 5, 9 /NL 4, 8 /NSQ 6 /OCT 5, 9 /P 5 /PTP 5 /SOL 6, 10 /WID 6, 11 1802 4, 34 3870 4 6502 4, 37 6800 4, 40 6805 4, 44 6809 4, 47 72, column 5 8008 4, 28 8048 4, 30 8080 4, 17 8085 4 ;, comment delimiter 59 <...> 59 = 59 ?, macro argument modifier 58 @, in command 3 @ 1, 59, 1, 59 .ABS 54 ABS 12 Absolute memory addressing 12 .ADDR 54 AMA 12 And, assembler operator 59 .ASCII 54 .ASCIZ 54 .ASECT 54 Index CROSS-Microcomputer cross assembler 69 ^B 1 \ 1 \ 58 ^B 59 \ 59 BEX, listing option 7 BIN extension 3 listing option 7 Binary listing option 7 Binary radix 1 .BLKB 54 .BLKW 54 .BYTE 54 Byte high 1 Low 1, 59 ^C 59 Card reader simulation 5 Catenation 15 CCL file 3 /CDR 5 CMUSW 65 CND, listing option 7 COM, listing option 7 Command line 3 Comment delimiter 59 listing option 7 Concatenation operator 58, 59 Conditional compilation: .IF 55 listing option 7 Contents, listing option 8 COSMAC COSMAC 1802 4, 34 Format 61 See also 1802 /CRF 5, 9 CRF.TMP file 9 Cross-reference 5 .CSECT 54 Current location counter 59 D 1, 59 Decimal radix 1 .DEPHAse 54 /DS 5, 12 .DSABL 5, 12, 54 DSK, device 3 Index CROSS-Microcomputer cross assembler 70 /EN 4, 12 .ENABL 4, 12, 54 .END 54 .ENDC 54 .ENDM 54 .ENDR 54 .EOT 54 /EQ 6 .EQUIV 54 ERF 12 .ERROR 54 Error flags, suppression 12 Error message suppression 5 Exorcisor Format 5, 62 $ 1, 59 % 1, 59 @ 1, 59 ^B 1, 59 ^C 59 ^H 1, 59 ^O 1, 59 \ 1 \ 58 \ 59 ^ 1, 59 Extension .BIN 3 .CCL 3 .LST 3 .M05 3 .M08 4 .M18 4 .M48 3 .M65 4 .M68 4 .M69 4 .M80 4 .M88 4 .MF8 4 .SML 14 F8 4 Fairchild F8 4 Floating point truncation 12 .FLT2 55 .FLT4 55 Formats COS 5, 61 COSMAC 5, 61 CP/M 5, 61 Exorcisor 5, 62 Index CROSS-Microcomputer cross assembler 71 Image binary 63 INT 5, 61 Intel 5, 61 Intellec 5, 61 KIM 5, 61 MOS 5 MOS Technology 5, 61 Mostek 61 MOT 5, 62 Motorola 5, 62 Packed binary 63 PTP 61 FPT 12 Generate new source 6, 10 .GLOBL 55 /GNS 6, 10 ^H 1, 59 Hex output 5, 61, 62 Hexadecimal radix 1 High byte 1 /I 5 .IF 55 .IFDF 55 .IFEQ 55 .IFF 55 .IFG 55 .IFGE 55 .IFGT 55 .IFL 55 .IFLE 55 .IFLT 55 .IFNDF 55 .IFNE 55 .IFNZ 55 .IFT 55 .IFTF 55 .IFZ 55 .IIF 55 Image mode output 5 Intel 8008 4, 28 8048 30 8080 4, 17 8085 4 MCS-48 4, 30 .IRP 55 .IRPC 56 KIM Index CROSS-Microcomputer cross assembler 72 Format 5, 61 See also 6502 LC 12 LD, listing option 8 /LEN 6, 10 /LI 4, 8 Libraries, macro 14 .LIMIT 56 Line numbers 6 .LIST 4, 7, 8, 56 Listing option BEX 7 BIN 7 CND 7 COM 7 LD 8 LOC 7 MB 7 MC 7 MD 7 ME 7 SEQ 7 SRC 7 SYM 8 TOC 8 TTM 8 LOC, listing option 7 .LOCAL 56 Location counter 59 Low byte 1, 59 Lower case 12 LPT, device 3 LSB 12 LST, extension 3 M05 /M05 switch 4 extension 3 M08 /M08 switch 4 extension 4 M18 /M18 switch 4 extension 4 M48 /M48 switch 4 extension 3 M65 /M65 switch 4 extension 4 M68 Index CROSS-Microcomputer cross assembler 73 /M68 switch 4 extension 4 M69 /M69 switch 4 extension 4 M80 /M80 switch 4 extension 4 M85 12 M88 /M88 switch 4 extension 4 .MACRO 56 Macro call listing option 7 Macro definition 56 Macro libraries 14 Macro, concatenation 58, 59 MB, listing option 7 MC, listing option 7 .MCALL 14, 56 MCS-48 4, 30 MD, listing option 7 ME, listing option 7 Memory addressing, absolute 12 .MEXIT 56 MF8 4 extension 4 MOS Technology 6502 4, 37 Mostek 3870 4 Motorola 6800 4, 40 6805 4, 44 6809 4, 47 /N 5, 9 .NARG 56 .NCHR 56 New source, generation 6, 10 /NL 4, 8 .NLIST 4, 7, 8, 56 See also ^C /NPP 12 /NSQ 6 .NTYPE 56 ^O 1, 59 See also Formats /OCT 5, 9 Octal radix 1, 5 Or, assembler operator 59 Index CROSS-Microcomputer cross assembler 74 Output format 5 /P 5 % 1, 59 Packed binary output 5 .PAGE 56 .PDP10 56 .PHASE 56 Phase error 47 .PRINT 56 .PSECT 56 /PTP 5 PTP, device 3 PTR, device 3 .RAD50 56 .RADIX 56 Radix 10 1 16 1 2 1 8 1, 5 binary 1 decimal 1 default 1 hexadecimal 1 octal 1 RCA 1802 4, 34 REG 12 Register %nn 1 .REM 57 .REPT 57 RIM, opcode 12 Rockwell 6502 37 .ROUND 12, 57 S1 record 62 S9 record 62 .SBTTL 57 SEQ, listing option 7 .SETDP 49, 57 SIM, opcode 12 Site-dependent CMU 65 Utah 65 /SOL 6, 10 Source listing option 7 Source, new, generation 6, 10 SRC, listing option 7 Suppression of error flags 12 Index CROSS-Microcomputer cross assembler 75 Switch CDR 5 CRF 5, 9 DS 5, 12 EN 4, 12 EQ 6 GNS 6, 10 I 5 LEN 6, 10 LI 4, 8 M05 4 M08 4 M18 4 M48 4 M65 4 M68 4 M69 4 M80 4 M88 4 N 5, 9 NL 4, 8 NPP 12 NSQ 6 OCT 5, 9 P 5 PTP 5 SOL 6, 10 WID 6, 11 SWITCH.INI 13 SYM, listing option 8 Symbol table listing option 8 Synertek 6502 37 SYSMAC.SML 14 Table of contents, listing option 8 Terminal format listing option 8 TIM 12 .TITLE 57 TOC, listing option 8 .TRUNC 12, 57 Truncation 12 TTM, listing option 8 TTY, device 3 ^ 1, 59 UTAHSW 65 /WID 6, 11 .WORD 57 Z80 4, 12, 21 Index CROSS-Microcomputer cross assembler 76 Z80 transliteration 23 Zilog Z80 4, 21 \, macro argument modifier 58 \ 58 \ 59 ^ 1 ^ 59 ^B 1, 59 ^C 59 ^H 1, 59 ^O 1, 59 | 15 Index CROSS-Microcomputer cross assembler i Table of Contents 1. Introduction 1 2. Syntax differences 2 3. Operating procedures 3 3.1. Loading CROSS 3 3.2. Initial dialogue 3 4. Listing control 7 4.1. Source statement listing control 7 4.2. Command string equivalents 8 4.3. Other listing controls 9 5. Enable/Disable control 12 6. User-defined switch defaults 13 7. Macro libraries 14 I. General notation 15 I.1. Machine State 15 I.2. Notation 15 I.3. Syntax 15 I.4. Opcodes 15 II. 8080 syntax 17 II.1. Machine State 17 II.2. Notation 17 II.3. Syntax 18 II.4. Opcodes 18 III. Z80 syntax 21 III.1. Introduction 21 III.2. Machine State 21 III.3. Notation 21 III.4. Opcodes 21 III.5. Z80 Transliterations 23 IV. 8008 28 Index CROSS-Microcomputer cross assembler ii IV.1. 8080 subset 28 V. 8048 30 V.1. Machine State 30 V.2. Notation 30 V.3. Syntax 31 V.4. Opcodes 31 VI. 1802 34 VI.1. Machine State 34 VI.2. Opcodes 34 VII. 6502 37 VII.1. Machine state 37 VII.2. Notation 37 VII.3. Syntax 38 VII.4. Opcodes 38 VIII. 6800 40 VIII.1. Machine State 40 VIII.2. Notation 40 VIII.3. Syntax 41 VIII.4. Opcodes 41 IX. 6805 44 IX.1. Machine State 44 IX.2. Notation 44 IX.3. Syntax 44 IX.4. Opcodes 45 X. 6809 47 X.1. Machine State 47 X.2. Notation 48 X.3. Syntax 48 X.4. Opcodes 49 XI. Compiler directives 54 XII. Macro quick summary 58 XIII. Assembler syntax quick summary 59 Index CROSS-Microcomputer cross assembler iii XIV. Error codes 60 XV. Object format 61 XV.1. PTP object format 61 XV.1.1. COSMAC format 61 XV.1.2. INT Format 61 XV.1.3. KIM Format 61 XV.1.4. MOT Format 62 XV.2. Binary file formats 62 XV.2.1. Packed binary file format 63 XV.2.2. Image binary file format 63 XV.2.3. Object format 63 XVI. Site-specific differences 65 Index 66 Index