.title	M9312 'MS' BOOT prom for TS11/TS04/TU80 compatible controller

	; This source code is an exact copy of the DEC M9312 23-764A9 boot PROM.
	;
	; This boot PROM is for any TS11 compatible tape controller.
	;
	; Multiple units and/or CSR addresses are supported via different entry points.
	;
	; Standard devices are 82S131, Am27S13, 74S571 or other compatible bipolar
	; PROMs with a 512x4 TriState 16pin DIP architecture. This code resides in
	; the low half of the device; the top half is blank and unused.
	;
	; Alternatively, 82S129 compatible 256x4 TriState 16pin DIP devices can be
	; used, as the uppermost address line (hardwired low) is an active low chip
	; select (and will be correctly asserted low).

tscsr	=172520				; std TS11 csrbase

tsdb	=+0-2				; data buffer reg offset
tssr	=+2-2				; command/status reg offset

diags	=165564				; console diags phase2 entry

	.asect
	.=173000

	; --------------------------------------------------

start:	.ascii	"SM"			; device code (reversed)

	.word	last-.			; offset to next boot header

ms0n:	sec				; boot std csr, unit zero, no diags
ms0d:	mov	#0,r0			; boot std csr, unit zero, with diags
msNr:	mov	#tscsr+2,r1		; boot std csr, unit <R0>
msNb:	mov	pc,r4			; boot csr <R1>, unit <R0>
	bcc	diag			; br if diags requested
	br	go			; return to (R4)+2 from diags
					; then skip over pseudo reboot vector

	; --------------------------------------------------

	.word	173000			; prom start addess @ 24
	.word	340			; and priority level @ 26

	; --------------------------------------------------

					;        cmd1:    cmd2:    cmd3:
pkt2:	.word	142010			; [1000] rewind   read     reread
	.word	0			; [1002] zero     addrlo   addrlo
	.word	0			; [1004]          addrhi   addrhi
	.word	512.			; [1006]          bytecnt  bytecnt

pkt1:	.word	140004			; [1010] set characteristics
	.word	1012			; [1012] addrlo
	.word	0			; [1014] addrhi

go:	mov	r0,r3			; [1016] copy unit ID
	mov	pc,r2			; [1020] mov #2$,r2: point at table
2$:	mov	#1022,r5		; ptr to memory buffer
3$:	mov	-(r2),-(r5)		; move table word to memory
	tstb	r5			; is low byte of address zero?
	bne	3$			; loop if not
					; R5=1000; R0=R3=unitID

	asl	r3			; unit ID times 4
	asl	r3			;
	add	r3,r1			; add to CSR base
	mov	r1,r2			; dup in R1,R2
	tst	-(r2)			; R1=tssr, R2=tsdb

4$:	tstb	(r1)			; check ready<7>
	bpl	4$			; loop if not ready

	clr	@#0			; zap memory loc 0
	mov	#1010,(r2)		; send command block at pkt1 (set char)

5$:	movb	(r1),r3			; get status, check ready<7>
	bpl	5$			; loop if not ready

6$:	mov	r5,(r2)			; send command block at pkt2 (rewind)

7$:	tstb	(r1)			; check ready<7>
	bpl	7$			; loop if not ready

	bit	#12,(r1)		; check if reg mod refused error
	bne	go			; br if set, must retry from start

	mov	#140001,(r5)		; change pkt2 command to read
	comb	r3			; invert status from above
	bpl	6$			; br if ready

8$:	mov	r5,(r2)			; send command block at pkt2 (read 512.)

9$:	tstb	(r1)			; check ready<7>
	bpl	9$			; loop if not ready

	tst	(r1)			; check error<15>
	bmi	10$			; br if error

	clr	pc			; jump to bootstrap at zero

10$:	mov	#161001,(r5)		; change pkt2 command to reread
	comb	r3			; invert status from above
	bpl	8$			; if no error, go reread block
	br	go			; else must retry from start

	; --------------------------------------------------

diag:	jmp	@#diags			; jump to console diags

	; --------------------------------------------------

	.word	0			; unused

	; --------------------------------------------------

	.=start+176
crc16:	.word	<140726>		; CRC-16 will go here

last:	; next boot prom starts here

	.end