                                                                                                                                                                          >>37<<5552 >>37<<///>>16<< >>37<<5552       44444  s>>37<<0              >>16<<///>>12<< >>16<<///>>16<< >>37<<242>>37<< >>37<<5552 >>17<<000>>17<< 11>>37<<11 >>37<<vv// >>37<<55>>15<<s                                               





                       PDP-1 COMPUTER
             ELECTRICAL ENGINEERING DEPARTMENT
           MASSACHUSETTS INSTITUTE OF TECHNOLOGY
                  CAMBRIDGE, MASSACHUSETTS
                           02139

















                           PDP-35


                     INSTRUCTION MANUAL


                PART 1 -- BASIC INSTRUCTIONS












                      9 September 1972


















                >>13<<0                                
          Introduction

     The  PDP-1 is a binary,  word-oriented digital computer.  It
has the ability to perform arithmetic upon numbers represented in
either  of  two  formats  known  as  one's  complement  and two's
complement respectively.  Two's complement is a relatively recent
addition  to the PDP-1 but it is the preferred mode of operation.
Therefore, this manual  will describe  in detail  only the  two's
complement  mode  of  operation.   However,  since  many existing
programs are written to run in one's complement mode, a brief but
complete  description of  one's complement  mode may  be found in
Appendix I.

     Although two's complement mode  is preferred, one's  comple-
ment mode is still the default mode of operation. To assemble and
debug a program to run in  two's mode, the following three  steps
must be taken>>40<<.

          1.  Place the  symbol "twos"   at the  beginning of the
          program that  >>34<<you  wish  to assemble.  This  tells  the
          assembler  that your  program is  to run in two's mode.

          2. Make "e2m"  the first instruction  of your  program.
          This  will set the computer  to run in two's complement
          mode.

          3. Type ">>04<<twos" to ID.  This tells ID that numbers  are
          represented in two's complement form. This need only be
          done once during each console session.




































                >>13<<)                                
1.        Basic Instructions

1.1       Word Formats

     Each PDP-1 word is 18 bits long.  The bits are numbered,  in
decimal, 0 to 17 from left to right.  In this manual, all numbers
are octal,  unless otherwise  specified.   The numbering  of  bit
positions in words is always decimal.



  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 
|   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
|         |         |         |         |         |         |

  first                                         last  
octal digit                                 octal digit


1.1.1     Number Formats

     The  entire word may be regarded  as a signed 18-bit number.
Bit 0 is the sign bit.  It is  on (i.e., a "1") if the number  is
negative. Positive numbers are represented in the ordinary binary
notation.  The range of positive numbers that can be  represented
is  0 to  377777 (131071 decimal).   The negative of  a number is
formed by complementing all bits of the number and then adding 1.
Hence  -1 is represented as  777777.  400000 (-131072 decimal) is
the most negative number that can be represented.  Note that  the
negative of 0 is 777777+1 which is 0.



































                >>13<<>>15<<                                
                            Examples

             Number (base 10)       Two's Complement

                   0                       0    
                   5                       5     
                  -5                  777773     
                 131071               377777     
                -131071               400001     
                -131072               400000     



     By  ignoring the sign convention,  a program could deal with
data words  as  unsigned numbers  ranging  between 0  and  262143
(decimal) or 0 and 777777 (octal).

     The  addition rule for 2 18-bit  numbers is as follows.  Add
the 2 numbers in the  normal fashion, propagating carries to  the
left.   If there  is a carry  out of the  last bit (bit  0) it is
ignored.  The addition is said to overflow if the result does not
correctly  represent  the  algebraically correct  sum,  i.e., the
magnitude of the correct result is greater than 377777.

     The overflow condition is equivalent to the condition that a
carry  occurred from  bit 1  but not  from bit  0 or  vice versa.


                 Example           Two's Complement

                      7                     7     
               >>40<<+   -10>>40<<0              >>40<<+ 77770>>40<<0     
                    -61                777707     


                 123456                123456     
               >>40<<+ 66666>>40<<6              >>40<<+ 66666>>40<<6     
                1012344       12344 = 1012344    



























                >>13<<a                                
1.1.2     Addressable Instruction Format

Instruction Part                  Address Part


  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

|  C  C  C  C  C|  I|  A  A  A  A  A  A  A  A  A  A  A  A|


Op. Code              1 of 4096 (decimal) locations

          the "i" bit



     The "instruction part" consists of  5 bits (the "op.  code")
that  tell which instruction the computer  will do if it executes
this word,  and  the  "i-bit"   which  has  to  do  with  address
modification.

     Except  for jmp   and  jsp, addressable  instructions take a
minimum  of  two  memory  cycles  --  one  to  fetch  the  actual
instruction and another to fetch the operand.  jmp and jsp do not
take an operand and consequently, require a minimum of one cycle.
The  amount of time required for  the execution of an addressable
instruction depends  on  what  addressing is  done  (see  PDP-35,
INSTRUCTION  MANUAL, Part 2 for complete information).  Under the
most common conditions, the actual time required for  instruction
execution is the minimum time given above.



1.1.6     Non-addressable Instruction Format


  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

|  C  C  C  C  C|  E  E  E  E  E  E  E  E  E  E  E  E  E|


Op. Code                  Extended Op. Code


The  low  13   bits are  actually an  extension of  the op. code,
further specifying what the  computer is to do.   Non-addressable
instructions  never require more  than one cycle  because they do
not reference memory, except for the ivk instruction with PRL  on
(See PDP-35, INSTRUCTION MANUAL, Part 5).
















                >>13<<b                                
1.2       Registers

     The PDP-1 contains 6 18-bit registers which define the state
of  the  user's  process.   They  are  the  A  (accumulator),   I
(input/output   register),  X   (index  register),   G,  F  (flag
register), and W.   When the  user first  logs in,  all of  these
registers  contain 0  (all bits  off).  This  defines the initial
state of the user's process.  Each of these registers has its own
properties.


1.2.1     Accumulator

     The  accumulator is the major register for use in processing
data. Most arithmetic and logical instructions operate on data in
A and leave results in A.


1.2.2     Input/Output Register

     The  input/output register was originally used primarily for
input/output operations.  This  is no  longer true.  I  is now  a
secondary accumulator. Many arithmetic and logical operations can
be performed on data contained in I.


1.2.3     Index Register

     The index register has two functions.  First, it is used  in
addressing  memory  (See  PDP-35,  INSTRUCTION  MANUAL,  Part 2).
Second, it is, like I, a secondary accumulator.


































                >>13<<w                                
1.2.4     G Register

     The G  register contains  the  15-bit program  counter,  the
overflow  bit, the extend mode bit,  and the arithmetic mode bit.

     The program counter (PC) is bits 3-17 of the G register. The
purpose  of the program counter is to tell the processor where in
memory the instruction  that is  to be executed  next lies.   The
program  counter is  incremented after  each instruction  so that
instructions  are  executed  sequentially,  according  to   their
locations  in memory.   When the program  counter is incremented,
carries out  of bit  6  of G  are  lost.  Thus,  the  instruction
executed   after  the   instruction  in  location   7777  is  the
instruction in location 0. Certain testing instructions increment
the  PC  an extra  time, causing  an  instruction to  be skipped.

     Bit 0 of G  is the overflow  bit (OVF).  It is  set to 1  by
certain arithmetic instructions when overflow occurs, and cleared
by the szo instruction.  Bit 1 of G is the extend mode bit (EXD).
This  bit is used in  addressing (See PDP-35, INSTRUCTION MANUAL,
Part 2).  Bit 2 of G is the arithmetic mode bit (TWOS).  If  this
bit  is off, the  processor is in one's  complement mode>>40<<, if this
bit it on, the processor is in two's complement mode.

     The format of the G register is shown below.

       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 

     |  O|  E|  T|  P  P  P  P  P  P  P  P  P  P  P  P  P  P  P|
     |  V|  X|  W|  C  C  C  C  C  C  C  C  C  C  C  C  C  C  C|
     |  F|  D|  O|  3  4  5  6  7  8  9  1  1  1  1  1  1  1  1|
     |   |   |  S|                       0  1  2  3  4  5  6  7|

































                >>13<<h                                
1.2.5     Flag Register

     The flag register contains the  6 program flags and  several
bits which define various states of the processor.

     The  program flags are 6 1-bit registers that may be quickly
and conveniently set and tested by programs (see Operate and Skip
class  instructions and also PDP-35,  INSTRUCTION MANUAL, Part 3,
section 3.2.6 concerning the light pen).

     The  3  bits  AMD,  AEF,  and  AAL  determine  the  mode  of
addressing  which the  processor will  use on  memory referencing
instructions (see PDP-35, INSTRUCTION MANUAL, Part 2).

     The 2 bits SBH (>>40<<Sequence >>40<<Break >>40<<Hold) and SBM (>>40<<Sequence >>40<<Break
>>40<<Mode)  determine the state of the sequence break system (see PDP-
35, INSTRUCTION MANUAL, Part 3).

     The  ESI  (>>40<<Execute  >>40<<Single   >>40<<Instruction)  bit  causes   the
processor to trap after each instruction is executed (see PDP-35,
INSTRUCTION MANUAL, Part 5).

     The PRL  (>>40<<Program >>40<<Reference  >>40<<List) bit  affects the  way  in
which the ivk (invoke) instruction works (see PDP-35, INSTRUCTION
MANUAL, Part 5).   When the PRL  bit is 1,  references to  memory
locations 0-77 are illegal.

     The format of the F register is as follows>>40<<.


       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

     |  A  A  A|  S  S|  P|  E|               |  P  P  P  P  P  P|
     |  M  E  A|  B  B|  R|  S|               |  F  F  F  F  F  F|
     |  D  F  L|  M  H|  L|  I|               |  1  2  3  4  5  6|



1.2.6     W Register

     The  W register, a software register maintained by the time-
sharing supervisor,  is used  solely for  communication with  the
supervisor. Certain mta and ivk instructions (both are supervisor
calls) use the W register  (see PDP-35, INSTRUCTION MANUAL,  Part
5).




















                >>13<<                                 
1.3       Instructions to Set the Arithmetic Mode


     The  PDP-1 processor may operate in either of two arithmetic
modes, one's complement and two's complement. The arithmetic mode
in which an instruction is executed is determined by the state of
the TWOS  bit  in the  G  register.  When  the  TWOS bit  is  off
(contains a 0), the processor is in one's complement mode.  One's
complement mode (TWOS  off) is the  default mode.  The  following
instructions change the state of TWOS.


Mnemonic  Op.Code  Name                Function

e2m       770060   Enter two's mode    Set TWOS to 1

e1m       770061   Enter one's mode    Set TWOS to 0



     The  instructions add,  adm, sub,  mul, div,  idx, isp, sft,
opr, and opr i (the micro-program instruction) behave differently
in one's and two's mode. Address arithmetic is always done in the
current arithmetic mode.









































                >>13<<>>35<<                                

1.4       Addressable Instructions

     In this section, the symbol "y" when used in the context  of
"ins  y" means the memory  location referenced by the instruction
"ins".  The notation "(y)" means the contents of location y.  For
information   on   how  addresses   are  computed,   see  PDP-35,
INSTRUCTION MANUAL, Part 2.



1.4.1     Data Moving Instructions

     These  instructions  serve  to  move  data  between   memory
locations and the A, I, and X registers.  These instructions copy
data words (or parts  of words) from one  place to the other  and
never destroy information at the source.



Mnemonic  Op.Code  Name                Function

lac y     20       load A              Copy (y) into A

lio y     22       load I              Copy (y) into I

lxr y     12       load X              Copy (y) into X

dac y     24       deposit A           Copy A into y

dio y     32       deposit I           Copy I into y

dap y     26       deposit address     Copy the low  12 bits of A
                   part of A           into y. The high 6 bits of
                                       y are unchanged

dip y     30       deposit instruc-    Copy the high  6 bits of A
                   tion part (of A)    into y. The low 12 bits of
                                       y are unchanged

dzm y     34       deposit zero in     Makes location y contain 0
                   memory























                >>13<<>>75<<                                
1.4.2     Logical Instructions


     These instructions take one operand in  A and the other from
a memory location.  The  result is left in   A.  Each bit of  the
result depends only on the corresponding bits of A and the memory
word before the operation.



                                       Each  bit of A will be a 1
                                       if and only if the corres-
                                       ponding bits in A  (before
                                       the instruction)  and  (y)
Mnemonic  Op.Code   Name               were --

and y     02        and                both one

ior y     04        inclusive          not both zero
                    or

xor y     06        exclusive          different
                    or










































                >>13<<f                                
1.4.3     Arithmetic Instructions


     The following  instructions are  used  to compute  sums  and
differences.  The "left" operand is in  A and the "right" operand
is taken from memory. The result is left in A  and in the case of
adm  (add  to memory),  it replaces  the  contents of  the memory
location as well.

     The overflow bit OVF   will be set by  the add, adm, or  sub
instructions if the signed result cannot be correctly represented
in 18 bits. This is the case if and only if a carry occurred from
bit one and no carry occurred from bit 0, or vice versa.  See the
szo  instruction.


Mnemonic  Op.Code  Name               Function

add y     40       add                Sum of A and (y) to A

adm y     36       add to memory      Sum of A and (y) to A and y

sub y     42       subtract           A minus (y) to A










































                >>13<<>>17<<                                
1.4.4     Multiply


     Multiply operates upon two  18 bit numbers  to produce a  36
bit product. mul may be viewed as multiplying two 17 bit integers
plus signs to produce a 35 bit integer plus sign in the  combined
A and I registers.


       0  1  2       16 17   0  1  2       16 17

sign |  >>40<< |   |   | >>40<<  >>40<<  >>40<< |   |   | |   |   |   | >>40<<  >>40<<  >>40<< |   |   |

                 A                     I
                                   least significant bit


     When two integers are multiplied such that the result can be
held in  one register,  the entire  result will  be in  I in  the
conventional signed integer format.

Examples --

                  >>40<<Before mu>>40<<l              >>40<<After mu>>40<<l

                 A          y            A         I

                 3       200000          0      600000
                -3       200000       777777    200000
                 3          2            0         6
                -3          2         777777    777772
              400000        2         777777       0
              400000     400000       200000       0



Mnemonic  Op.Code  Name               Function

mul y     54       multiply           A times (y) to A,I


     Multiply takes a minimum of two memory cycles plus from 3 to
15 microseconds, depending on the number of one's in A.






















                >>13<<3                                
1.4.5   Divide


     Divide (div) takes a double-length integer in  A  and  I (in
the  format produced by mul) and  divides this by a single length
integer in the addressed memory location. The result of a div  is
a  single-length  integer  quotient  in  A,  and  a single-length
integer remainder in I.   The sign of the  remainder will be  the
same as that of the dividend.

     If  a quotient overflow occurs, that is, if the divisor goes
into the  dividend more  times  than can  be represented  in  the
accumulator (A), the div instruction will not skip. If a div does
not skip, the contents of the A and I registers are preserved  if
the divisor is 0, otherwise they are usually destroyed. div never
sets the overflow bit.


                            Examples


      >>40<<Before divid>>40<<e                       >>40<<After divid>>40<<e

   A        I       C(Y)                  A        I

   0       16         2                   7        0
   0        7         3                   2        1
   0       11      777773                -1        4
   0       25      777774                -5        1
   1     400000    200000                 6        0
777776   377777    777774              300000     -1
777777      0      400000                 2        0
200000      0      400000              400000      0
   6      777776      0              no skip,  A and
                                         I unchanged
100000   222222    100000            no skip,  A and
                                         I destroyed


Mnemonic  Op.Code  Name               Function

div y     56       divide             Quotient of (A,I)/(y) to A
                                      Remainder to I
                                      Skip  if the  quotient does
                                      not overflow


     Divide instructions  which  skip  take two  cycles  plus  20
microseconds.   Divide instructions which restore  A and I and do
not skip take 2 cycles>>40<<, other non-skipping divides take 2  cycles
plus 20 microseconds.














                >>13<<g                                
1.4.6     Counting Instructions


     The two instructions  idx  and  isp  add one (in the current
arithmetic mode) to the contents of the specified memory location
and  leave the result both in memory  and A.  isp  skips the next
instruction if the result is positive.  Neither instruction  will
set overflow.



Mnemonic  Op.Code  Name              Function

idx y     44       index             (y) + 1  to  A  and  y

isp y     46       index and skip    (y) + 1  to  A  and  y
                   if result positive      skip if result >>40<<> 0




1.4.7     Compare Instructions


     The  following two instructions are  used to compare A  with
the contents of a memory loction.  The comparison is done bit-by-
bit, therefore, the contents of A are the same as the contents of
memory if  and  only  if every  bit  of  A is  the  same  as  the
corresponding bit in memory.




Mnemonic  Op.Code  Name and Function

sas y     52       skip if A is the same as (equal to) the
                   contents of y

sad y     50       skip if A is different from (y)


























                >>13<<8                                
1.4.8     Transfer of Control


     All  of  the  following  instructions  have  the  effect  of
changing the program counter (PC)  so that the  PDP-1 will  begin
executing instructions in a new sequence.



Mnemonic  Op.Code  Name              Function

jmp y     60       jump              transfer control to location
                                     y

jdp y     14       jump and deposit  store G in y, jump to y+1
                   program counter

jsp y     62       jump and save     jump to y and save G in A
                   program counter   

jda y     17       jump and deposit  store A in y,  save  G in A,
                   accumulator       jump to y+1 (dac y, jsp y+1)

cal y     16       call              store A in 00100,  save G in
                                     A,  jump to 00101, y ignored
                                     (similar to jda 100)


     The  instructions  jdp, jsp,  and jda  are used  chiefly for
calling  subroutines.   The  saved  G  register  is  the  linkage
mechanism which allows the subroutine to return to the place from
which it was called.


                         Simple Examples


          jdp subr              jsp subr              jda subr
            ...                   ...                   ...


   subr,  0              subr,  dap subx       subr,  0
            ...                   ...                 dap subx
            ...                   ...                   ...
          jmp i subr     subx,  jmp            subx,  jmp
 


     These examples show three ways in which a subroutine may  be
called.   In  each example  the  method by  which  the subroutine
returns to the calling program  is illustrated.  In each  example
the   return  is  to  the   location  immediately  following  the
subroutine call.












                >>13<<                                 
1.4.9     Execute


     The  xct  instruction causes  the contents of the  specified
memory  location  to be  executed as  an instruction.   xct's may
execute other  xct's.  In all cases the effect is the same as  if
the  xct were replaced by the instruction it addresses. xct takes
a minimum  of  one  cycle  plus the  time  to  do  the  addressed
instruction.



Mnemonic  Op.Code  Name              Function

xct y     10       execute           execute the contents of y as
                                     an instruction

















































                >>13<<>>56<<                                
1.5       Non-Memory Referencing Instructions

1.5.1     Skip Class


     Instructions  from the skip  class will cause  the  PDP-1 to
jump over  one instruction  in the  normal sequence  if the  skip
condition  described by  the low  13 bits  of the  instruction is
true.


A skip class instruction has the following format --


  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

|  1  1  0  1  0|  I|  S  S  S  S  S  S  S  S  S  S  S  S|


Op. Code 64=skp              skip conditions

          invert sense of skip



     Each of the low 12 bits enables a different skip  condition.







































                >>13<<y                                Mnemonic  Op.Code  Name                Function

skp       640000   skip                never skips

szf n     64000n   skip on zero        skip if program flag n is
                   flag n (1>>40<<<n>>40<<<7)      off.  szf 7  skips if all
                                       flags are off.

szs n0    6400n0   skip on zero        skip if  sense switch n is
                   switch n (1>>40<<<n>>40<<<7)    off.  szs 70  skips if all
                                       switches are off.

sza       640100   skip on zero A      skip if A(0-17) = 0

spa       640200   skip on positive A  skip if A(0) = 0

sma       640400   skip on minus A     skip if A(0) = 1

szo       641000   skip on zero        skip  if the  overflow bit
                   overflow            (OVF) is off.
                                       A  szo  instruction always
                                       clears OVF

spi       642000   skip on positive I  skip if I(0) = 0

sni       644000   skip on nonzero I   skip if I(0-17) |= 0


     If  more than one skip condition is enabled, the instruction
skips if any  (i.e. the  logical OR)  of the  skip conditions  is
true.

     The  "i-bit" reverses  the sense of  the skip,  i.e., a skip
instruction with the  "i-bit" on  will skip  if and  only if  the
corresponding  instruction with  the "i-bit" off  would not skip.
For example, skp 4200 will skip if either I |= 0 or A(0) = 0.  skp
i 4200 will not skip if either of these conditions is true. Thus,
skp i 4200 will skip only if I = 0 and A(0) = 1.

     The following mnemonics define several useful compound  skip
instructions,  i.e,  each  has several  skip  conditions enabled.



Mnemonic  Op.Code  Name                Function

szm       640500   skip on zero or     skip if A(0-17) = 0  or if
                   minus accumulator   A(0) = 1
                                       (szm = sma>>05<<sza)

spq       650500   skip on positive    skip if  A > 0
                   quantity            (spq = sma>>05<<sza i)

clo       651600   clear overflow      this  never  skips>>40<<,  it is
                                       used to clear overflow
                                       (clo = spa>>05<<sma>>05<<szo i)










                >>13<<n                                
1.5.2     Shift/Rotate Class


     The  shift  instruction  offers  a  very  powerful  set   of
operations  including  rotates,  logical  and  arithmetic shifts,
normalization, and bit counting.  The register operated upon  may
be the A, I, AI (bit 17 of A joined to bit 0 of I), or IA (bit 17
of I joined to bit 0 of A). The A and I registers may be operated
upon independently.

     Shift is an arithmetic operation. Shifting a number left one
bit position is equivalent  to multiplying it  by two.  A  single
right shift divides a number by two. The sign bit does not change
during a shift.  During right shifts, the sign bit is  propagated
to  the  right.   During  left  shifts,  zeroes  are  shifted in.

     Rotate is  a logical  operation  during which  the  register
being  shifted is considered to be  a ring where bits leaving one
end are brought into the vacated  bit position at the other  end.



  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

|  1  1  0  1  1|  A  A  A  A|  I  I  I  I|  C  C  C  C  C|

Op.Code 66=sft
                  A field     I field        Count


The 4 bits of the A and I fields are interpreted as follows>>40<<.

                            | D| R| R| R|

            D = direction>>40<<.  0 => right      1 => left
            RRR = operation>>40<<.     decoded as follows>>40<<. 

0>>40<<.
          If  direction  = right,  do  nothing to  this register.
          If direction =  left, zeroes are  shifted into bit  17,
          bit 0 is unchanged>>40<<, if bit lost from bit 1 |= bit 0, set
          overflow (arithmetic shift left).

1>>40<<.
          If direction = right, see below.
          If direction  = left,  bit 0  of opposite  register  is
          shifted  into bit 17,  bit 0 is  unchanged>>40<<, if bit lost
          from bit 1 |= bit 0, set overflow (arithmetic shift left
          combined).

2>>40<<.
          Shift zeroes into vacated bit (logical shift).













                >>13<<0                                
3>>40<<.
          Shift ones into vacated bit.

4>>40<<.
          Shift bit 0 of this register into vacated bit.

5>>40<<.
          Shift  bit  17  of  this  register  into  vacated  bit.

6>>40<<.
          Shift bit  0 of  opposite  register into  vacated  bit.

7>>40<<.
          Shift  bit 17  of opposite  register into  vacated bit.


If A field = 01, then>>40<<.

          If the I  field is 00,  10, or 11,  then shift I  until
          either  I(0)  |= I(1)  or the  count  runs out.   A will
          contain  the  number  of  places  shifted  (Normalize).

          If  the I field is not 00, 10, or 11, then I will shift
          as usual. A will contain the number of ones shifted out
          of I(17)  (Count Bits).

          Note>>40<<.   A is first  cleared and then  counts during the
          operation, hence I field = 11 will shift in zeroes just
          as I field = 10 does.


   I field = 01 is reserved for future expansion.



   The  number of positions  to move the  selected register(s) is
determined by the number in the 5 bit count field.  If the  count
field is 0, the count is taken from X(13-17).

   Execution time = 1 cycle + (count-5)x0.2 microsecond

























                >>13<<l                                
USAGE

   ID  and  the  assembler  consider  certain  symbols consisting
entirely  of  upper   case  letters  to   be  two's  mode   shift
instructions.

   The  symbols specifying shift/rotate  operations are formed as
follows>>40<<.


        <direction field><function field><register field>


<direction field>
          The direction field  indicates the  direction in  which
          the  selected  register  is  to  be  moved.   The  only
          permissable  contents  of  this  field  are  R  or   L,
          specifying right and left motion, respectively.


<function field>
          The  function field  determines what  is to  be shifted
          into the bit position that  is vacated as the  selected
          register  is moved.  This field must contain one of the
          symbols F>>40<<, G,  Z (>>40<<Zeroes), O  (>>40<<Ones), P (>>40<<Propagate),  R
          (>>40<<Rotate), V (re>>40<<Verse bits), C (>>40<<Combined), or S (>>40<<Shift).


        Function field       Operation Bits

                    Direction=Left    Direction=Right

           F                 0            0
           G                 1            1
           Z (Zeroes)        2            2
           O (Ones)          3            3
           P (Propagate)     5            4
           R (Rotate)        4            5
           V (reVerse bits)  7            6
           C (Combined)      6            7
           S (Shift)         0            4
























                >>13<<3                                <register field>
          The register field selects the register which is to  be
          operated upon. The register field may contain either an
          A, I, C, R, or N.  C, R, and N are defined in terms  of
          more  basic operations.  In the definitions, "a" stands
          fo either R or L.  "b" stands for either F, G, Z, O, P,
          R, V, C, or S.

          A indicates the A register.

          I indicates the I register.

          C  indicates the combined  A and I  registers (AI).  In
          this mode,  bit  17 of  A  is joined  to  bit 0  of  I.
                 LSC => LGA>>05<<LZI>>40<<, aRC => aCA>>05<<aCI
                 LbC => LCA>>05<<LbI>>40<<, RbC => RbA>>05<<RCI

          R  indicates  the reverse  combined  I and  A registers
          (IA).  In this mode, bit 17 of I is joined to bit 0  of
          A.
                 LbR => LbA>>05<<LCI>>40<<, RbR => RCA>>05<<Rb>>40<<I
                 LSR => LZA>>05<<LGI>>40<<, aRR => aCA>>05<<aCI

          N  indicates that  the operation  to be  performed is a
          normalize or count bits operation.
                         abN => RGA>>05<<abI








































                >>13<<>>16<<                                
                            EXAMPLES


OPERATION          A           I           AI          IA

shift left         LSA         LSI         LSC         LSR
shift right        RSA         RSI         RSC         RSR
rotate left        LRA         LRI         LRC         LRR
rotate right       RRA         RRI         RRC         RRR
logical left       LZA         LZI         LZC         LZR
logical right      RZA         RZI         RZC         RZR


count bits in I     RZN 18.
normalize I         LSN 17.


   Two rotate/shift operations, one moving  only A and the  other
only  I may be  combined into one  instruction by logically ORing
together the instruction moving A  and that moving I.  Both  ORed
instructions must share the same count.


                            EXAMPLES


shift A right 3>>40<<, shift I left 3                RSA>>05<<LSI 3
rotate A left 7>>40<<, shift I right 7               LRA>>05<<RSI 7
copy reversed bits of I into A                 LVA>>05<<RRI 18.
clear A and I                                  RZI>>05<<RZA 18.
reverse 36 bits of AI                          LVA>>05<<RVI 18.


































                >>13<<0                                
1.5.3     The  law  Instruction


   law  and  law i  ("load accumulator with") make it possible to
load the accumulator with 12 bit positive or negative numbers  in
one cycle.


  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

|  1  1  1  0  0|  I|  N  N  N  N  N  N  N  N  N  N  N  N|


Op.Code 70=law        12-bit number to be loaded

          on to complement



   law first loads A from the address part of the instruction and
then, if the i-bit is on, complements A. Thus,  law 3  puts three
into A  and  law i 3  puts  777774  into A.

   lan ("load accumulator with negative") is defined as law 7777.
Thus, lan n (1 >>40<<< n >>40<<< 10000) will load A with -n.








































                >>13<<g                                1.5.4     The Operate Class

   Each bit of the address part of an opr instruction enables  an
operation in the processor.


  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

|  1  1  1  1  1  0|  E  E  E  E  E  E  E  E  E  E  E  E|

                    c  l  c  c  c  c  l  l  s
                    l  a  m  s  l  m  a  i  t
                    i  t  a  a  a  i  i  a  f


Op.Code 76 = opr          operation enabling bits


   Several  operations can be enabled by turning on more than one
bit in  the  address  part.   The  order  in  which  the  various
operations on  A  and I  occur is -- first, clear A  and clear I>>40<<,
second, OR in the test word>>40<<, third, negate A>>40<<, fourth,  complement
A   and complement  I>>40<<,  and last, switch data between  A  and  I.


Mnemonic  Op.Code  Name                Function

opr       760000

nop       760000   no operation        one cycle time delay

stf n     76001n   set flag n          set one of the six program
                   (1>>40<<<n>>40<<<7)             flags. Set all if n=7. Set  
                                       none if n=0

clf n     76000n   clear flag n        clear selected flag. Clear
                   (1>>40<<<n>>40<<<7)             all if n=7.  Clear none if
                                       n=0

lia       760020   load I from A       make I the same as A

lai       760040   load A from I       make A the same as I

swp       760060   swap A and I        exchange the contents of A
                                       and I

cmi       760100   complement I        invert all the bits of I

cla       760200   clear A             put 0 into A

csa       760400   complement and      negate A.   If A contained
                   step A              400000, OVF is set.














                >>13<<>>14<<                                
cma       761000   complement A        invert all the bits of A

clc       761200   clear and           put 777777 in A
                   complement A

csc       761400   complement, step,   subtract 1 from A
                   and complement A

          762000   OR test word to A

lat       762200   load test word      copy  test  word  switches
                                       into A

cli       764000   clear I             put 0 into I



   Although the  stf  and  clf  instructions are usually used  to
manipulate  the program flags,  there are also  the following two
instructions --


Mnemonic  Op.code  Name                Function

lpf       770051   load program flags  Top 2 bits of I to Address
                                       mode bits.   Bottom 6 bits
                                       of I to program flags.

rpf       770050   read program flags  Address mode to top 3 bits
                                       of I.  Flags to low 6 bits
                                       of I.


































                >>13<<>>35<<                                
1.5.7     The Micro-program Class


   The  micro-program   instruction  class   has  the   following
instruction format --



  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17

|  1  1  1  1  1  1|  X  X|  Y  Y  Y|  A  A  A|  S  S  S  S|


Op.Code 77                               skip conditions

      operands (column in      assignment of result
       following table)

                  operation (row in following table)



           Symbolic Specification of Micro-program Operations

   XX    00        01        10        11
YYY
     |      I   |          |          |          |
000  |      N   |    TI    |    TA    |    TX    |   T (Test, or transfer)
     |   S  S   |          |          |          |
     |   P  T   |          |          |          |
001  |   E  R   |    NI    |    NA    |    NX    |   N (Negate)
     |   C  U   |          |          |          |
     |   I  C   |    A>>20<<I   |    X>>20<<A   |    X>>20<<I   |   exchange (see
010  |   A  T   |    (I)   |    (A)   |    (I)   |     explanation below)
     |   L  I   |          |          |          |
     |      O   |          |          |          |
011  |      N   |    AMI   |    XMA   |    XMI   |   M (arithmetic minus)
     |      S   |          |          |          |
     |    Z     |          |          |          |
100  |  (zero)  |    A>>05<<I   |    X>>05<<A   |    X>>05<<I   |   >>05<< (inclusive or)
     |          |          |          |          |
     |    SA    |          |          |          |
101  |  (A)+1   |    A>>06<<I   |    X>>06<<A   |    X>>06<<I   |   >>06<< (bitwise and)
     |          |          |          |          |
     |    SI    |          |          |          |
110  |  (I)+1   |    A~I   |    X~A   |    X~I   |   ~ (exclusive or)
     |          |          |          |          |
     |    SX    |          |          |          |
111  |  (X)+1   |    A+I   |    X+A   |    X+I   |   + (arithmetic plus)
     |          |          |          |          |


        S (Step, i.e., add one)












                >>13<<,                                     The functions  of the  result assignment  and skip condition
fields are as follows --

AAA       Bit 11=1 will put the result in A
          Bit 12=1  "    "   "     "    " I
          Bit 13=1  "    "   "     "    " X

SSSS      Bit 14=1>>40<<. Skip if the result is   > 0
          Bit 15=1>>40<<.  "   "   "    "    "    <-1
          Bit 16=1>>40<<.  "   "   "    "    "    = 0
          Bit 17=1>>40<<.  "   "   "    "    "    =-1


   The execution  of  a micro-program  instruction  computes  the
result specified by the XX  and  YYY bits (i.e. from the Table on
the previous page), puts this result in the specified register(s)
if  any, and skips  if any of the  specified conditions are true.
Note that the skip  condition is evaluated on  the result of  the
micro-program,  not the final contents of any given register, and
the result need  not be assigned  to any register.   Thus, it  is
possible to test the sum of A  and I to see if it is greater than
0  without  destroying  the  contents of  these  registers.   The
instruction  to do this  is  773610, or  symbolically, A+I>.  All
micro-program instructions require one cycle.

   The "T"  operation clears  the transmitted register after  the
transfer.   This may be circumvented by assigning the result back
to the transmitted register.  See the examples.

   The exchange operation is a special case.  The result A>>20<<I  (I)
means  that the result of the function is the old I register, but
in addition  the  accumulator is  placed  in I.   This  secondary
assignment is done before the assignment given by the AAA bits in
the instruction. Thus, the instruction  A>>20<<I  (772400) will move A
to  I, A>>20<<IA  (772500) will swap  A and I, and  A>>20<<II (772440) does
nothing (because the primary assignment is to I and the result is
the old  I).

   The  instructions add and  subtract will turn  on the overflow
bit if the addition or subtraction overflows. Stepping 377777 and
negating 400000 also set overflow.

























                >>13<<>>76<<                                
USAGE

   The  assembler considers certain symbols consisting of capital
letters as  micro-program instructions.   The entire  instruction
must  be in upper  case, and may appear  in any expression, e.g.,
storage word, constant, etc. When typing into ID, the instruction
must be preceded by a single quote (').

   Micro-program  instructions  are  specified  by  concatenating
three "fields" -- the result field, the assignment field, and the
skip field.  The characters in all of these must be in upper case
and there must be no separator between the fields.


          <result field><assignment field><skip field>


<result field>
                    The result field must  be one of the  twenty-
                    eight   results  given  in  the  table  on  a
                    previous page.  "C" may  be used in place  of
                    "N" (negate).

<assignment field>
                    The  assignment field  may be  null (no char-
                    acters) or any combination of A, I, and X  to
                    specify in which registers the result will be
                    placed.

<skip field>
                    The skip  field may  be null  or contain  any
                    combination  of  <, >,  P, M,  | ,  >>40<< ,  and =.


                    Symbol    Meaning>>40<<.       Two's

                    >      skip if result    >0
                    P      skip if result    =0
                    M      skip if result    =-1
                    <      skip if result    <0
                    =      skip if result    =0
                    >>40<<       skip if result    =0
                    <M     skip if result    <-1
                    |       invert the specified skip conditions

   Since the octal representation of a micro-program  instruction
is  computed by exclusive-or'ing all of the specifications within
each field,  redundant  specifications  may  lead  to  unexpected
results.   For example, TAIII  and  TAI>>   are the same as  TAI.
















                >>13<<>>16<<                                
                SAMPLE MICRO-PROGRAM INSTRUCTIONS


symbolic  octal    action

I+A       773600   computes sum of  A and  I  and does nothing at
                   all with it.

A+IA      773700   the sum of A and I is put into A.

A+IAIX    773760   the sum of A and I is put into A, I, and X.

ZAIX      771160   A, I, and X are cleared.

SA>       771210   skip if A plus one is > 0.

SAAP      771302   add one to (step) A and skip if it is 0.

TXM       776001   skip if X is -1 and clear X.

TXXM      776021   skip if X is -1.

TAXI      774060   transfer the contents of A into I and X,  then
                   clear A.

TAAXI     774160   same as TAXI, but A is not cleared.

A>>20<<IA      772500   exchange the contents of A and I.

X>>20<<A>P     774412   transfer the contents of X into A, skip if the
                   previous A is positive.

SAM       771201   skip if  A plus one  is -1.

A+I<P     773607   skip if the sum of A and I is >>40<<< 0.

A+I<P|     773610   skip if the sum of A and I is > 0.

A+IX>>40<<>     773632   the sum of A and I is put into X.   If the sum
                   is >>40<<> 0,  the instruction will skip.

NXP       776202   skip is X is 0.























                >>13<<)                                                                                                     
