listing instructions lines are 65 chracters long. set paper edge at 7 on flexo. set margin at 18. >>13<<6 PDP-1 COMPUTER ELECTRICAL ENGINEERING DEPARTMENT MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139 PDP-35 INSTRUCTION MANUAL PART 2 -- ADDRESS CALCULATION December 12, 1971 >>13<<>>16<< 2.0 Address Calculation A direct or unmodified data address is calculated by concatenating the Extended Program Counter (the EPC is bits 3-5 of the G register) and the address part of the instruction. core 1 EPC PC 1-0104 1 0106 1-0105 201234 (lac 1234) 1-0106 1 1234 data address 1-1234 data Addresses may also be deferred (indirected), indexed, or both (in either order). These operations are said to "modify" the address specified by the address part of the instruction. 2.1 Indirect Addresses Under certain conditions an instruction may specify that its address is indirect or deferred. This means that, instead of addressing the data directly, its address part gives the address of a location which contains a "pointer" to (address of) the data location. Each defer cycle takes one extra memory cycle. >>13<<>>13<< 2.1.1 Indirect Addresses Out of Extend Mode If the computer is not in extend mode (EXD is off), multiple level indirect addressing may be used, but the instruction, all defer cycles, and the final execute cycle will be in the same core memory module. After each defer cycle, the i-bit (bit 5) of the word read from memory is examined. If it is on, another defer cycle occurs at the address given by the address part of the word. If the i-bit is off, the indirect chain terminates and the address part is used as the actual data address. core 2 EPC PC 2-0003 211234 lac i 1234 2 0004 2-0004 normal mode extend off 2 1234 indirect addr. 2-1234 052105 i-bit on 2 2105 indirect addr. 2-2105 013224 i-bit on 2 3224 indirect addr. 2-3224 004256 i-bit off 2 4256 data address 2-4256 data >>13<

>13<>13<<6 2.2.2 Indexing a Deferred Address A deferred address may also be indexed. If the computer is not in extend mode, the address part of the deferred address and the EPC are used. If EXD is on, the low 15 bits of the deferred address are used. Indexing of indirect addresses applies only on the last defer cycle. deferred addr. index register QAAAAA XXXXXX EXD=1 EXD=0 EPC INDEX ADDER [0-2] [3-5] [6-17] discard core address >>13<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<

>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>13<<1 2.3.2 Base Mode In base mode the index register usually points to the base of a "private block" associated with the specific process that is executing reentrant code. All addressable instructions (except jump-type instructions) are indexed into the private block. Base mode is identical to alternated normal mode. In base mode AMD is off and AEF is on. Base mode is entered by executing a >>40<>40<>13<<, 2.3.3 Index and Defer Modes An >>40<>40<>40<>40<>13<< 2.4 Examples 2.4.1 Normal Mode or Alternated Base Mode bam nam aam lac 30 OR lac 30 >>40<< >>40<< >>40<< >>40<< >>40<< >>40<< 30/ 105 30/ 105 The accumulator is loaded from location 30 of the current core. No index or defer happens. bam nam aam lac i 30 OR lac i 30 >>40<< >>40<< >>40<< >>40<< >>40<< >>40<< 30/ 10105 30/ 10105 105/ 1234 105/ 1234 1234/ 3 1234/ 3 10105/ 6 10105/ 6 If the computer is not in extend mode, A is loaded with 3 after two defers. If EXD is on, a single extended defer happens, picking up the 6 from core 1. >>13<<3 2.4.2 Base Mode or Alternated Normal Mode Assume X has +10 in it. nam bam aam lac 30 OR lac 30 >>40<< >>40<< >>40<< >>40<< >>40<< >>40<< 30/ 105 30/ 105 40/ 21 40/ 21 The effective address is 30+(contents of X) = 40. Thus, 21 is put into A. Assume X contains 777770. nam bam aam lac 70 OR lac 70 . . . . . . 60/ 105 60/ 105 61/ 144 61/ 144 70/ -10 70/ -10 The effective address is 70+(contents of X). This sum differs in one's and two's mode. In one's mode, the effective address is 61 and therefore 144 is put into A. In two's mode, the effective address is 60 and accordingly 105 is placed into A. Assume X has 10100 in it and the same program is in core 2. If the machine is not in extend mode, the index address is relative to the current core (2). Thus, the effective address is 20000+10100+30=30130 or location 30 of core 3. If EXD is on, the effective address is 10130 or location 130 of core 1. >>13<<>>13<< Consider the following program in core 2 with 10100 in X. 10130/ 31234 10130/ 31234 20007/ nam 20010/ bam 20010/ aam lac i 30 lac i 30 >>40<< >>40<< >>40<< >>40<< >>40<< >>40<< 30130/ 11234 30130/ 11234 31234/ 62345 31234/ 62345 32345/ 6 32345/ 6 Out of extend mode, a defer chain is started at (address part) + (index register) + (current core) = 130 of core 3. Two defers happen and 6 is finally loaded into the accumulator. In extend mode a single extended defer is done through core 1 location 130. This location points to core 3 location 1234, so that 62345 is put into A. >>13<>40<< >>40<< >>40<< 30/ 105 No index or indirect modifications happen. The accumulator is loaded with 105. Assume the following program is in core 2 and X has 10100 in it. 10130/ 6 20010/ iam /or dam 20011/ lac i 30 >>40<< >>40<< >>40<< 30130/ 11 Only indexing can happen. Out of extend mode the effective address is (contents of X) + (address part) + (current core) = 30130 or location 130 of core 3. Eleven is put into A. In extend mode the reference will be to 10130 or location 130 of core 1. Six will be put into A. >>13<>40<< >>40<< >>40<< 30/ 10105 105/ 01234 1234/ 3 11234/ 6 /core 1 No indexing occurs, but the instruction defers through location 30 of the same core. If EXD is on, this is an extended defer and the accumulator gets loaded with 6. If EXD is off, two defers happen and A picks up the 3 from location 1234. Assume X has 10100 in it and the following program is in core 2. 10130/ 31234 20010/ iam 20011/ aam 20012/ lac i 30 >>40<< >>40<< >>40<< 30130/ 11234 31234/ 62345 32345/ 6 In index mode indexing happens before defering. Thus, out of extend mode a two-level defer chain is started at location 130 of core 3. This ends by loading the accumulator with 6. In extend mode a single extended defer is done through 130 of core 1, and A is loaded with 62345. >>13<<4 2.4.5 Alternated Defer Mode dam aam lac 30 >>40<< >>40<< >>40<< 30/ 10105 105/ 01234 1234/ 3 10105/ 6 /core 1 No indexing occurs. Out of extend mode, the instruction defers through location 30 and again through 105, resulting in 3 being put into the accumulator. In extend mode, a single defer causes the 6 in location 105 of core 1 to be loaded. In the next program assume that core 2 is current and the index register contains 10100. 11234/ 17730 20010/ dam 20011/ aam 20012/ lac i 30 >>40<< >>40<< >>40<< 20030/ 11234 21234/ 2345 21334/ 3 32445/ 6 In alternated defer mode defers happen before indexing. Thus, out of extend mode, the >>40<>40<<0 will defer twice, resulting in 2345 which will be added to the index register and current core(2), resulting in a final effective address of core 3 location 2445. Six would be loaded into A. With EXD on, a single defer happens through 30 of core 2. Then 11234 is added to the index register, giving a final address of 21334. Therefore, the accumulator is loaded with 3. >>13<<>>60<< 2.5 Instructions that Affect Effective Address Calculation Mnemonic Op. Code Function nam 770052 enter normal address mode bam 770053 enter base address mode iam 770054 enter index (first) address mode dam 770055 enter defer (first) address mode aam 770056 cause 1-instruction mode change eem 770046 enter extend mode lem 770047 leave extend mode lpf 770051 loads AMD, AEF, AAL from I[0-2]. See section 1.3.4 However- AAL will be turned off at the end of this instruction. >>13<<0 2.6 Sample Programs The following are examples of uses of the various address modes and the index register. 2.6.1 Exchange Array Contents The following program segment exchanges the contents of two arrays, named >>40<>40<<1 and >>40<>40<<2. Both are 400 words long. In this example the index register is used both as a counter and an increment into the arrays. /runs in either iam or dam /the -400 below should be considered in the same arithmetic / mode as that in which the program runs exchng, lxr (-400 /minus the length to X next, lac i array1+400 /pick up the words lio i array2+400 dio i array1+400 /put back exchanged dac i array2+400 SXXZ /add 1 to X,skip if up to 0 jmp next /not done done, >>40<< >>40<< >>40<< array1+0/ array2+0/ array1+1/ X array2+1/ array1+2/ array2+2/ >>40<< >>40<< >>40<< >>40<< >>40<< >>40<< array1+377/ array2+377/ >>13<< 'x>>06<>13<<.