>>37<<5552 >>37<>16<< >>37<<5552 44444 s>>37<<0 >>16<>12<< >>16<>16<< >>37<<242>>37<< >>37<<5552 >>17<<000>>17<< 11>>37<<11 >>37<>37<<55>>15<>13<<0 Introduction The PDP-1 is a binary, word-oriented digital computer. It has the ability to perform arithmetic upon numbers represented in either of two formats known as one's complement and two's complement respectively. Two's complement is a relatively recent addition to the PDP-1 but it is the preferred mode of operation. Therefore, this manual will describe in detail only the two's complement mode of operation. However, since many existing programs are written to run in one's complement mode, a brief but complete description of one's complement mode may be found in Appendix I. Although two's complement mode is preferred, one's comple- ment mode is still the default mode of operation. To assemble and debug a program to run in two's mode, the following three steps must be taken>>40<<. 1. Place the symbol "twos" at the beginning of the program that >>34<>04<>13<<) 1. Basic Instructions 1.1 Word Formats Each PDP-1 word is 18 bits long. The bits are numbered, in decimal, 0 to 17 from left to right. In this manual, all numbers are octal, unless otherwise specified. The numbering of bit positions in words is always decimal. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | | | | | | | | | | | | | | | | | | | | | | | | | | first last octal digit octal digit 1.1.1 Number Formats The entire word may be regarded as a signed 18-bit number. Bit 0 is the sign bit. It is on (i.e., a "1") if the number is negative. Positive numbers are represented in the ordinary binary notation. The range of positive numbers that can be represented is 0 to 377777 (131071 decimal). The negative of a number is formed by complementing all bits of the number and then adding 1. Hence -1 is represented as 777777. 400000 (-131072 decimal) is the most negative number that can be represented. Note that the negative of 0 is 777777+1 which is 0. >>13<<>>15<< Examples Number (base 10) Two's Complement 0 0 5 5 -5 777773 131071 377777 -131071 400001 -131072 400000 By ignoring the sign convention, a program could deal with data words as unsigned numbers ranging between 0 and 262143 (decimal) or 0 and 777777 (octal). The addition rule for 2 18-bit numbers is as follows. Add the 2 numbers in the normal fashion, propagating carries to the left. If there is a carry out of the last bit (bit 0) it is ignored. The addition is said to overflow if the result does not correctly represent the algebraically correct sum, i.e., the magnitude of the correct result is greater than 377777. The overflow condition is equivalent to the condition that a carry occurred from bit 1 but not from bit 0 or vice versa. Example Two's Complement 7 7 >>40<<+ -10>>40<<0 >>40<<+ 77770>>40<<0 -61 777707 123456 123456 >>40<<+ 66666>>40<<6 >>40<<+ 66666>>40<<6 1012344 12344 = 1012344 >>13<>13<>13<>40<<, if this bit it on, the processor is in two's complement mode. The format of the G register is shown below. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | O| E| T| P P P P P P P P P P P P P P P| | V| X| W| C C C C C C C C C C C C C C C| | F| D| O| 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1| | | | S| 0 1 2 3 4 5 6 7| >>13<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<>40<<. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | A A A| S S| P| E| | P P P P P P| | M E A| B B| R| S| | F F F F F F| | D F L| M H| L| I| | 1 2 3 4 5 6| 1.2.6 W Register The W register, a software register maintained by the time- sharing supervisor, is used solely for communication with the supervisor. Certain mta and ivk instructions (both are supervisor calls) use the W register (see PDP-35, INSTRUCTION MANUAL, Part 5). >>13<< 1.3 Instructions to Set the Arithmetic Mode The PDP-1 processor may operate in either of two arithmetic modes, one's complement and two's complement. The arithmetic mode in which an instruction is executed is determined by the state of the TWOS bit in the G register. When the TWOS bit is off (contains a 0), the processor is in one's complement mode. One's complement mode (TWOS off) is the default mode. The following instructions change the state of TWOS. Mnemonic Op.Code Name Function e2m 770060 Enter two's mode Set TWOS to 1 e1m 770061 Enter one's mode Set TWOS to 0 The instructions add, adm, sub, mul, div, idx, isp, sft, opr, and opr i (the micro-program instruction) behave differently in one's and two's mode. Address arithmetic is always done in the current arithmetic mode. >>13<<>>35<< 1.4 Addressable Instructions In this section, the symbol "y" when used in the context of "ins y" means the memory location referenced by the instruction "ins". The notation "(y)" means the contents of location y. For information on how addresses are computed, see PDP-35, INSTRUCTION MANUAL, Part 2. 1.4.1 Data Moving Instructions These instructions serve to move data between memory locations and the A, I, and X registers. These instructions copy data words (or parts of words) from one place to the other and never destroy information at the source. Mnemonic Op.Code Name Function lac y 20 load A Copy (y) into A lio y 22 load I Copy (y) into I lxr y 12 load X Copy (y) into X dac y 24 deposit A Copy A into y dio y 32 deposit I Copy I into y dap y 26 deposit address Copy the low 12 bits of A part of A into y. The high 6 bits of y are unchanged dip y 30 deposit instruc- Copy the high 6 bits of A tion part (of A) into y. The low 12 bits of y are unchanged dzm y 34 deposit zero in Makes location y contain 0 memory >>13<<>>75<< 1.4.2 Logical Instructions These instructions take one operand in A and the other from a memory location. The result is left in A. Each bit of the result depends only on the corresponding bits of A and the memory word before the operation. Each bit of A will be a 1 if and only if the corres- ponding bits in A (before the instruction) and (y) Mnemonic Op.Code Name were -- and y 02 and both one ior y 04 inclusive not both zero or xor y 06 exclusive different or >>13<>13<<>>17<< 1.4.4 Multiply Multiply operates upon two 18 bit numbers to produce a 36 bit product. mul may be viewed as multiplying two 17 bit integers plus signs to produce a 35 bit integer plus sign in the combined A and I registers. 0 1 2 16 17 0 1 2 16 17 sign | >>40<< | | | >>40<< >>40<< >>40<< | | | | | | | >>40<< >>40<< >>40<< | | | A I least significant bit When two integers are multiplied such that the result can be held in one register, the entire result will be in I in the conventional signed integer format. Examples -- >>40<>40<>40<>40<>13<<3 1.4.5 Divide Divide (div) takes a double-length integer in A and I (in the format produced by mul) and divides this by a single length integer in the addressed memory location. The result of a div is a single-length integer quotient in A, and a single-length integer remainder in I. The sign of the remainder will be the same as that of the dividend. If a quotient overflow occurs, that is, if the divisor goes into the dividend more times than can be represented in the accumulator (A), the div instruction will not skip. If a div does not skip, the contents of the A and I registers are preserved if the divisor is 0, otherwise they are usually destroyed. div never sets the overflow bit. Examples >>40<>40<>40<>40<>40<<, other non-skipping divides take 2 cycles plus 20 microseconds. >>13<>40<<> 0 1.4.7 Compare Instructions The following two instructions are used to compare A with the contents of a memory loction. The comparison is done bit-by- bit, therefore, the contents of A are the same as the contents of memory if and only if every bit of A is the same as the corresponding bit in memory. Mnemonic Op.Code Name and Function sas y 52 skip if A is the same as (equal to) the contents of y sad y 50 skip if A is different from (y) >>13<<8 1.4.8 Transfer of Control All of the following instructions have the effect of changing the program counter (PC) so that the PDP-1 will begin executing instructions in a new sequence. Mnemonic Op.Code Name Function jmp y 60 jump transfer control to location y jdp y 14 jump and deposit store G in y, jump to y+1 program counter jsp y 62 jump and save jump to y and save G in A program counter jda y 17 jump and deposit store A in y, save G in A, accumulator jump to y+1 (dac y, jsp y+1) cal y 16 call store A in 00100, save G in A, jump to 00101, y ignored (similar to jda 100) The instructions jdp, jsp, and jda are used chiefly for calling subroutines. The saved G register is the linkage mechanism which allows the subroutine to return to the place from which it was called. Simple Examples jdp subr jsp subr jda subr ... ... ... subr, 0 subr, dap subx subr, 0 ... ... dap subx ... ... ... jmp i subr subx, jmp subx, jmp These examples show three ways in which a subroutine may be called. In each example the method by which the subroutine returns to the calling program is illustrated. In each example the return is to the location immediately following the subroutine call. >>13<< 1.4.9 Execute The xct instruction causes the contents of the specified memory location to be executed as an instruction. xct's may execute other xct's. In all cases the effect is the same as if the xct were replaced by the instruction it addresses. xct takes a minimum of one cycle plus the time to do the addressed instruction. Mnemonic Op.Code Name Function xct y 10 execute execute the contents of y as an instruction >>13<<>>56<< 1.5 Non-Memory Referencing Instructions 1.5.1 Skip Class Instructions from the skip class will cause the PDP-1 to jump over one instruction in the normal sequence if the skip condition described by the low 13 bits of the instruction is true. A skip class instruction has the following format -- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | 1 1 0 1 0| I| S S S S S S S S S S S S| Op. Code 64=skp skip conditions invert sense of skip Each of the low 12 bits enables a different skip condition. >>13<>40<<>40<<<7) off. szf 7 skips if all flags are off. szs n0 6400n0 skip on zero skip if sense switch n is switch n (1>>40<<>40<<<7) off. szs 70 skips if all switches are off. sza 640100 skip on zero A skip if A(0-17) = 0 spa 640200 skip on positive A skip if A(0) = 0 sma 640400 skip on minus A skip if A(0) = 1 szo 641000 skip on zero skip if the overflow bit overflow (OVF) is off. A szo instruction always clears OVF spi 642000 skip on positive I skip if I(0) = 0 sni 644000 skip on nonzero I skip if I(0-17) |= 0 If more than one skip condition is enabled, the instruction skips if any (i.e. the logical OR) of the skip conditions is true. The "i-bit" reverses the sense of the skip, i.e., a skip instruction with the "i-bit" on will skip if and only if the corresponding instruction with the "i-bit" off would not skip. For example, skp 4200 will skip if either I |= 0 or A(0) = 0. skp i 4200 will not skip if either of these conditions is true. Thus, skp i 4200 will skip only if I = 0 and A(0) = 1. The following mnemonics define several useful compound skip instructions, i.e, each has several skip conditions enabled. Mnemonic Op.Code Name Function szm 640500 skip on zero or skip if A(0-17) = 0 or if minus accumulator A(0) = 1 (szm = sma>>05< 0 quantity (spq = sma>>05<>40<<, it is used to clear overflow (clo = spa>>05<>05<>13<>40<<. | D| R| R| R| D = direction>>40<<. 0 => right 1 => left RRR = operation>>40<<. decoded as follows>>40<<. 0>>40<<. If direction = right, do nothing to this register. If direction = left, zeroes are shifted into bit 17, bit 0 is unchanged>>40<<, if bit lost from bit 1 |= bit 0, set overflow (arithmetic shift left). 1>>40<<. If direction = right, see below. If direction = left, bit 0 of opposite register is shifted into bit 17, bit 0 is unchanged>>40<<, if bit lost from bit 1 |= bit 0, set overflow (arithmetic shift left combined). 2>>40<<. Shift zeroes into vacated bit (logical shift). >>13<<0 3>>40<<. Shift ones into vacated bit. 4>>40<<. Shift bit 0 of this register into vacated bit. 5>>40<<. Shift bit 17 of this register into vacated bit. 6>>40<<. Shift bit 0 of opposite register into vacated bit. 7>>40<<. Shift bit 17 of opposite register into vacated bit. If A field = 01, then>>40<<. If the I field is 00, 10, or 11, then shift I until either I(0) |= I(1) or the count runs out. A will contain the number of places shifted (Normalize). If the I field is not 00, 10, or 11, then I will shift as usual. A will contain the number of ones shifted out of I(17) (Count Bits). Note>>40<<. A is first cleared and then counts during the operation, hence I field = 11 will shift in zeroes just as I field = 10 does. I field = 01 is reserved for future expansion. The number of positions to move the selected register(s) is determined by the number in the 5 bit count field. If the count field is 0, the count is taken from X(13-17). Execution time = 1 cycle + (count-5)x0.2 microsecond >>13<>40<<. The direction field indicates the direction in which the selected register is to be moved. The only permissable contents of this field are R or L, specifying right and left motion, respectively. The function field determines what is to be shifted into the bit position that is vacated as the selected register is moved. This field must contain one of the symbols F>>40<<, G, Z (>>40<>40<>40<>40<>40<>40<>40<>13<<3 The register field selects the register which is to be operated upon. The register field may contain either an A, I, C, R, or N. C, R, and N are defined in terms of more basic operations. In the definitions, "a" stands fo either R or L. "b" stands for either F, G, Z, O, P, R, V, C, or S. A indicates the A register. I indicates the I register. C indicates the combined A and I registers (AI). In this mode, bit 17 of A is joined to bit 0 of I. LSC => LGA>>05<>40<<, aRC => aCA>>05< LCA>>05<>40<<, RbC => RbA>>05< LbA>>05<>40<<, RbR => RCA>>05<>40< LZA>>05<>40<<, aRR => aCA>>05< RGA>>05<>13<<>>16<< EXAMPLES OPERATION A I AI IA shift left LSA LSI LSC LSR shift right RSA RSI RSC RSR rotate left LRA LRI LRC LRR rotate right RRA RRI RRC RRR logical left LZA LZI LZC LZR logical right RZA RZI RZC RZR count bits in I RZN 18. normalize I LSN 17. Two rotate/shift operations, one moving only A and the other only I may be combined into one instruction by logically ORing together the instruction moving A and that moving I. Both ORed instructions must share the same count. EXAMPLES shift A right 3>>40<<, shift I left 3 RSA>>05<>40<<, shift I right 7 LRA>>05<>05<>05<>05<>13<<0 1.5.3 The law Instruction law and law i ("load accumulator with") make it possible to load the accumulator with 12 bit positive or negative numbers in one cycle. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | 1 1 1 0 0| I| N N N N N N N N N N N N| Op.Code 70=law 12-bit number to be loaded on to complement law first loads A from the address part of the instruction and then, if the i-bit is on, complements A. Thus, law 3 puts three into A and law i 3 puts 777774 into A. lan ("load accumulator with negative") is defined as law 7777. Thus, lan n (1 >>40<<< n >>40<<< 10000) will load A with -n. >>13<>40<<, second, OR in the test word>>40<<, third, negate A>>40<<, fourth, complement A and complement I>>40<<, and last, switch data between A and I. Mnemonic Op.Code Name Function opr 760000 nop 760000 no operation one cycle time delay stf n 76001n set flag n set one of the six program (1>>40<<>40<<<7) flags. Set all if n=7. Set none if n=0 clf n 76000n clear flag n clear selected flag. Clear (1>>40<<>40<<<7) all if n=7. Clear none if n=0 lia 760020 load I from A make I the same as A lai 760040 load A from I make A the same as I swp 760060 swap A and I exchange the contents of A and I cmi 760100 complement I invert all the bits of I cla 760200 clear A put 0 into A csa 760400 complement and negate A. If A contained step A 400000, OVF is set. >>13<<>>14<< cma 761000 complement A invert all the bits of A clc 761200 clear and put 777777 in A complement A csc 761400 complement, step, subtract 1 from A and complement A 762000 OR test word to A lat 762200 load test word copy test word switches into A cli 764000 clear I put 0 into I Although the stf and clf instructions are usually used to manipulate the program flags, there are also the following two instructions -- Mnemonic Op.code Name Function lpf 770051 load program flags Top 2 bits of I to Address mode bits. Bottom 6 bits of I to program flags. rpf 770050 read program flags Address mode to top 3 bits of I. Flags to low 6 bits of I. >>13<<>>35<< 1.5.7 The Micro-program Class The micro-program instruction class has the following instruction format -- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | 1 1 1 1 1 1| X X| Y Y Y| A A A| S S S S| Op.Code 77 skip conditions operands (column in assignment of result following table) operation (row in following table) Symbolic Specification of Micro-program Operations XX 00 01 10 11 YYY | I | | | | 000 | N | TI | TA | TX | T (Test, or transfer) | S S | | | | | P T | | | | 001 | E R | NI | NA | NX | N (Negate) | C U | | | | | I C | A>>20<>20<>20<>05<>05<>05<>05<< (inclusive or) | | | | | | SA | | | | 101 | (A)+1 | A>>06<>06<>06<>06<< (bitwise and) | | | | | | SI | | | | 110 | (I)+1 | A~I | X~A | X~I | ~ (exclusive or) | | | | | | SX | | | | 111 | (X)+1 | A+I | X+A | X+I | + (arithmetic plus) | | | | | S (Step, i.e., add one) >>13<<, The functions of the result assignment and skip condition fields are as follows -- AAA Bit 11=1 will put the result in A Bit 12=1 " " " " " I Bit 13=1 " " " " " X SSSS Bit 14=1>>40<<. Skip if the result is > 0 Bit 15=1>>40<<. " " " " " <-1 Bit 16=1>>40<<. " " " " " = 0 Bit 17=1>>40<<. " " " " " =-1 The execution of a micro-program instruction computes the result specified by the XX and YYY bits (i.e. from the Table on the previous page), puts this result in the specified register(s) if any, and skips if any of the specified conditions are true. Note that the skip condition is evaluated on the result of the micro-program, not the final contents of any given register, and the result need not be assigned to any register. Thus, it is possible to test the sum of A and I to see if it is greater than 0 without destroying the contents of these registers. The instruction to do this is 773610, or symbolically, A+I>. All micro-program instructions require one cycle. The "T" operation clears the transmitted register after the transfer. This may be circumvented by assigning the result back to the transmitted register. See the examples. The exchange operation is a special case. The result A>>20<>20<>20<>20<>13<<>>76<< USAGE The assembler considers certain symbols consisting of capital letters as micro-program instructions. The entire instruction must be in upper case, and may appear in any expression, e.g., storage word, constant, etc. When typing into ID, the instruction must be preceded by a single quote ('). Micro-program instructions are specified by concatenating three "fields" -- the result field, the assignment field, and the skip field. The characters in all of these must be in upper case and there must be no separator between the fields. The result field must be one of the twenty- eight results given in the table on a previous page. "C" may be used in place of "N" (negate). The assignment field may be null (no char- acters) or any combination of A, I, and X to specify in which registers the result will be placed. The skip field may be null or contain any combination of <, >, P, M, | , >>40<< , and =. Symbol Meaning>>40<<. Two's > skip if result >0 P skip if result =0 M skip if result =-1 < skip if result <0 = skip if result =0 >>40<< skip if result =0 > are the same as TAI. >>13<<>>16<< SAMPLE MICRO-PROGRAM INSTRUCTIONS symbolic octal action I+A 773600 computes sum of A and I and does nothing at all with it. A+IA 773700 the sum of A and I is put into A. A+IAIX 773760 the sum of A and I is put into A, I, and X. ZAIX 771160 A, I, and X are cleared. SA> 771210 skip if A plus one is > 0. SAAP 771302 add one to (step) A and skip if it is 0. TXM 776001 skip if X is -1 and clear X. TXXM 776021 skip if X is -1. TAXI 774060 transfer the contents of A into I and X, then clear A. TAAXI 774160 same as TAXI, but A is not cleared. A>>20<>20<P 774412 transfer the contents of X into A, skip if the previous A is positive. SAM 771201 skip if A plus one is -1. A+I

>40<<< 0. A+I 0. A+IX>>40<<> 773632 the sum of A and I is put into X. If the sum is >>40<<> 0, the instruction will skip. NXP 776202 skip is X is 0. >>13<<)