PDP-1 COMPUTER MODIFICATION BULLETIN no. 2 The PDP-1 computer now is equipped with a high speed magnetic drum storage. The drum is divided into 22 fields of 4096 words each. Words are transferred between the drum and the core memory under automatic control. Because the drum runs at 30 revolutions per second, each word on the drum is available once every 33-1/3 milliseconds_, but when a drum operation has begun, words are transferred at a rate of 8.16 microseconds each. In one operation, information can be written on the drum, read from the drum, or both written and read simultaneously. Each field has a five bit address and each word in a given field has a twelve bit address. By use of the instructions below, the programmer specifies a drum field, an initial word address, an initial core memory address, the number of words to be transferred, and whether the operation is to write on the drum, read from the drum, or swap the contents of core memory with the contents of the drum. The following instructions have been added to the PDP-1_. DIA (iot 60) - [drum initial address] Causes the C(IO) bits 1-5 to be sent to the drum write field buffer. These bits specify which field of the drum will be written on during the next DCC instruction_, or, if C(IO) bits 1-5=0, that no write operation is to occur. The C(IO) bits 6-17 are sent to the drum initial address register to specify the first drum address to be transferred. DBA (iot 61) [drum break on address] Causes the C(IO) bits 6-17 to be sent to the drum initial address register. When the current drum address becomes equal to the contents of the initial address register a sequence break request is initiated. Bit 5 of the status word is set by the break, and is cleared by the next DCC instruction. DCC (iot 62) [drum count and commence] Causes the C(IO) bits 1-5 to be sent to the drum read field buffer. These bits specify which field will be read_, or, if C(IO) bits 1-5 = 0, that no read operation is to occur. The C(AC) bits 6-17 specify the first core memory address of the data to be transferred. The C(IO) bits 6-17 specify the number of words to be transferred. If the C(IO) bits 6-17 = 0, 4096 words are transferred. While the DCC instruc- tion is being executed, the computer stops and the drum system takes full control of the core memory. Successive words are transferred from sequential locations until the operation is complete. If no errors occurred during the drum operation, the instruction following the DCC is skipped. The C(AC) and C(IO) are lost during this operation. If both the read field and the write field are non-zero (both read and write operations are specified) the contents of memory are written on the write field_, then the read field data are read into memory. The read field must not equal the write field. In order to avoid passing a given drum address, and hence losing 33 milliseconds, the DCC instruction must be given at least 250 microseconds before the drum address reaches the initial address. DRA (iot 63) [drum read address] Causes the current drum address to be read into IO bits 6-17. The parity error flag is read into IO bit 0_, and the timing error flag is read into IO bit 2. Two cycles elapse before this information is placed in the IO. ERROR CONDITIONS The drum will be a major component of the forthcoming PDP- 1 Time Sharing System described in memo PDP-6. Because several fields will be needed for the time sharing system, users are requested to use the lower numbered fields when possible. 2